HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: M13S128324A-6BG (No company)

Modify typing error of Pin Arrangement

 

Download: PDF   ZIP
No company

Document Outline

ESMT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 1/48
Revision History
Revision 0.1 (May. 13 2005)
-Original

Revision 0.2 (Aug. 08 2005)
-Delete Non-Pb-free of ordering information
-Modify typing error of Pin Arrangement

Revision 1.0 (Mar. 0
8 2006)
-Delete "Preliminary" at every page
-Modify tWR from 2clk to 15ns
-Modify tWTR from 1clk to 2ns
ESMT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 2/48
DDR SDRAM
1M x 32 Bit x 4 Banks
Double Data Rate SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data access per clock cycle
Bi-directional data strobe (DQS)
On-chip DLL
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2; 2.5; 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, full page
Full page burst length for sequential burst type only
Start address of the full page burst should be even
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)
DQS is edge-aligned with data for reads; center-aligned with data for WRITE
Data mask (DM) for write masking only
V
DD
= 2.375V ~ 2.625V, V
DDQ
= 2.375V ~ 2.625V
Auto & Self refresh
32ms refresh period (4K cycle)
SSTL-2 I/O interface
144Ball FBGA package
Operating Frequencies :
PRODUCT NO.
MAX FREQ
VDD
PACKAGE
COMMENTS
M13S128324A -5BG
200MHz
2.5V
144 Ball FBGA
Pb-free
M13S128324A -6BG
166MHz
2.5V
144 Ball FBGA
Pb-free
ESMT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 3/48
Control Logic
Functional Block Diagram




Pin Arrangement
144(12x12) FBGA
Bank A
Command Deco
der
Bank D
Latch Circuit
Bank B
Bank C
DM
DQ
Mode Register &
Extended Mode
Register
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Row Decode
r
Sense Amplifier
Column Decoder
Data Control Circuit
Input & Out
put
Buf
fer
Address
Clock
Generator
CLK
CLK
CKE
CS
RAS
CAS
WE
DLL
DQS
CLK, CLK
DQS
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
VSSQ
DM3
DQ28
DQS3
DQ4
VDDQ
VDDQ
DQ1
DQ30
NC
VDDQ
NC
VDDQ
VDDQ
DQ6
DQ5
VSSQ
DQ7
VSSQ
VDD
VDDQ
VSSQ
DQ26
VSS
VSSQ
DQ27
VDD
VSS
VDD
VDDQ
VSS
DQ25
DQ17
DQ16
VSSQ
VSS
Thermal
DQ19
VDDQ
DQ18
DQS2
VDDQ
DM2
DQ15
DQ24
VDDQ
DQ13
DQ21
NC
DQ14
DQ20
NC
DM1
DQ12
VDDQ
VDDQ
DQ11
DQS1
DQ22
DQ23
VSS
VSS
VSS
CAS
VDDQ
VSS
RAS
VDDQ
NC
DQ9
VSS
VSSQ
A10
BA1
DQ10
VDD
A2
NC
A9
VDD
VDD
VDD
A5
NC
CS
NC
NC
VSS
DQ8
NC
CK
A0
NC
A1
NC
A4
A6
BA0
A3
CKE
A7
VREF
WE
2
3
4
5
6
7
8
9
10
11
12
13
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VDDQ
VDD
VSS
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSSQ
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSSQ
VSSQ
VSSQ
VSSQ
A8/AP
CK
NC
B
C
D
E
F
G
H
J
K
L
M
N
A11
ESMT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 4/48
Pin Description
(M13S128324A)
Pin Name
Function
Pin Name
Function
A0~A11,
BA0,BA1
Address inputs
- Row address A0~A11
- Column address A0~A7
A8/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DM0~DM3
DQ Mask enable in write cycle.
DQ0~DQ31 Data-in/Data-out
CLK, CLK
Clock input
RAS
Row address strobe
CKE
Clock enable
CAS
Column address strobe
CS
Chip select
WE
Write enable
V
DDQ
Supply Voltage for GDQ
V
SS
Ground V
SSQ
Ground for DQ
V
DD
Power
V
REF
Reference Voltage for SSTL
DQS0~DQS3
Bi- directional Data Strolle.
DQS0 correspond to the data on DQ0~DQ7.
DQS1 correspond to the data on DQ8~DQ15.
DQS2 correspond to the data on DQ16~DQ23.
DQS3 correspond to the data on DQ24~DQ31.
NC
No
connection




































ESMT
M13S128324A
Elite Semiconductor Memory Technology Inc.
Publication Date : Mar. 2006
Revision : 1.0 5/48




Absolute Maximum Rating
Parameter Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 3.6
V
Voltage on V
DDQ
supply relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
TBD W
Short circuit current
I
OS
50 mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications

DC Operation Condition

Recommended operating conditions (Voltage reference to V
SS
= 0V, T
A
= 0 to 70 C
)
Parameter Symbol
Min
Max
Unit
Note
Supply voltage
V
DD
2.375 2.625 V
I/O Supply voltage
V
DDQ
2.375 2.625 V
I/O Reference voltage
V
REF
0.49*V
DDQ
0.51*V
DDQ
V 1
I/O Termination voltage (system)
V
TT
V
REF
- 0.04
V
REF
+ 0.04
V
2
Input logic high voltage
V
IH
(DC) V
REF
+ 0.15
V
DDQ
+ 0.3
V
Input logic low voltage
V
IL
(DC) -0.3 V
REF
- 0.15
V
Input leakage current
I
I
-5 5
A
3
Output leakage current
I
OZ
-5 5
A
Output High Current (Normal strength driver)
(V
OUT
=V
DDQ
-0.373V, min V
REF
, min V
TT
)
I
OH
-16.8 mA
Output Low Current (Normal strength driver)
(V
OUT
= 0.373V)
I
OL
+16.8 mA
Output High Current (Weak strength driver)
(V
OUT
=V
DDQ
-0.763V, min V
REF
, min V
TT
)
I
OH
-9 mA
Output Low Current (Weak strength driver)
(V
OUT
= 0.763V)
I
OL
+9 mA
Notes 1. V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V
REF
may not exceed 2% of the DC value.
2. V
TT
is not applied directly to the device. V
TT
is system supply for signal termination resistors, is expected to be set equal
to V
REF
, and must track variations in the DC level of V
REF
.
© 2018 • ICSheet
Contact form
Main page