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Datasheet: M12L64322A (No company)

512k X 32 Bit X 4 Banks Synchronous Dram

 

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No company
ESMT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
1/44
SDRAM
512K x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6s refresh interval
ORDERING INFORMATION

86 Pin TSOP (TypeII)
(400mil x 875mil)


Product No.
MAX FREQ.
PACKAGE
M12L64322A-6T
166MHz
M12L64322A-7T
143MHz
TSOPII

GENERAL DESCRIPTION

The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.
Synchronous design allows precise cycle control wi0th the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.

PIN ARRANGEMENT
Top View
1
2
3
4
5
6
7
8
9
V
DD
DQ0
V
D D Q
DQ1
DQ2
V
S S Q
DQ3
DQ4
V
D D Q
86
85
84
83
82
81
80
79
78
66
65
64
63
62
61
60
59
58
V
S S
DQ15
V
S S Q
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S S Q
10
11
12
13
14
15
16
17
18
19
20
DQ5
DQ6
V
S S Q
DQ7
N C
V
D D
DQ M 0
W E
CAS
RAS
C S
77
76
75
74
73
72
71
70
69
68
67
DQ10
DQ9
V
DD Q
DQ8
N C
V
S S
DQ M 1
N C
N C
CLK
CK E
N C
DQ31
V
D D Q
DQ30
DQ29
V
S S Q
DQ28
DQ27
V
D D Q
DQ26
DQ25
V
S S Q
DQ24
V
S S
21
22
23
24
25
26
27
28
29
N C
BA0
BA1
A10/AP
A0
A1
A2
D QM 2
V
DD
30
31
32
33
34
35
36
37
38
39
N C
DQ16
V
S S Q
DQ17
DQ18
V
D D Q
DQ19
DQ20
V
S S Q
DQ21
DQ22
40
41
42
43
V
DD Q
DQ23
V
D D
A9
A8
A7
A6
A5
A4
A3
DQ M 3
V
S S
57
56
55
54
53
52
51
50
49
48
47
46
45
44
86 Pin TSOP (II )
(4 0 0 mi l x 8 7 5m i l )
(0 .5 mm Pin pit ch )
ESMT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
2/44
DQM0~3
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decode
r
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Out
put
Buf
f
er
Address
Clock
Generator
CLK
CKE
Command Deco
der
CS
RAS
CAS
WE
BLOCK DIAGRAM














PIN DESCRIPTION
PIN NAME
INPUT
FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A10
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA10, column address : CA0~CA7
BA0 , BA1
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
ESMT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
3/44
PIN NAME
INPUT
FUNCTION
DQM0~3
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ DQ31
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
V
DD
/ V
SS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
V
DDQ
/ V
SSQ
Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C
No Connection
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70 C
)
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0 3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DD
+0.3 V
1
Input logic low voltage
V
IL
-0.3 0 0.8 V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
= -2mA
Output logic low voltage
V
OL
- - 0.4 V
I
OL
= 2mA
Input leakage current
I
IL
-5 - 5
A
3
Output leakage current
I
OL
-5 - 5
A
4
Note: 1. V
IH
(max) = 4.6V AC for pulse width
10ns acceptable.
2.
V
IL
(min) = -1.5V AC for pulse width
10ns acceptable.
3. Any input 0V
VIN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4. Dout is disabled , 0V
V
OUT
V
DD
.
ESMT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
4/44
CAPACITANCE (V
DD
= 3.3V, T
A
= 25
C
, f = 1MHZ)
Parameter Symbol
Min
Max
Unit
Input capacitance (A0 ~ A10, BA0 ~ BA1)
CIN1
2
4
pF
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE & DQM)
CIN2 2 4 pF
Data input/output capacitance (DQ0 ~ DQ31)
COUT
2
5
pF
DC CHARACTERISTICS
Recommended operating condition unless otherwise notedT
A
= 0 to 70 C
Version
Parameter
Symbol Test
Condition
CAS
Latency
-6 -7
Unit
Note

Operating Current
(One Bank Active)
I
CC1
Burst Length = 1
t
RC
t
RC(min)
I
OL
= 0 mA
160
140
mA
1,2
I
CC2P
CKE
V
IL
(max), tcc = 15ns
2
Precharge Standby Current
in power-down mode
I
CC2PS
CKE & CLK
V
IL
(max), t
cc
=
2
mA
I
CC2N
CKE
V
IH
(min), CS
V
IH
(min), t
cc
= 15ns
Input signals are changed one time during 30ns
30
Precharge Standby Current
in non power-down mode
I
CC2NS
CKE
V
IH
(min), CLK
V
IL
(max), t
cc
=
input signals are stable
10

mA
I
CC3P
CKE
V
IL
(max), tcc = 15ns
10
Active Standby Current
in power-down mode
I
CC3PS
CKE & CLK
V
IL
(max), t
cc
=
10
mA
I
CC3N
CKE
VIH(min), CS
V
IH
(min), tcc = 15ns
Input signals are changed one time during 30ns
40 mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3NS
CKE
V
IH
(min), CLK
V
IL
(max), tcc =
input signals are stable
10 mA
3 250
220

Operating Current
(Burst Mode)
I
CC4
IOL = 0 mA
Page Burst
2 Banks activated
2 200
180
mA
1,2
Refresh Current
I
CC5
t
RC
t
RC(min)
310 285 mA
Self Refresh Current
I
CC6
CKE
0.2V
2 mA
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
ESMT
M12L64322A
Elite Semiconductor Memory Technology Inc.
Publication Date: May. 2004
Revision: 1.7
5/44
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V 0.3V T
A
= 0 to 70 C
)
Parameter Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol
-6 -7
Unit Note
Row active to row active delay
t
RRD(min)
12 14 ns 1
RAS to CAS delay
t
RCD(min)
18 18 ns 1
Row precharge time
t
RP(min)
18 20 ns 1
t
RAS(min)
42 42 ns 1
Row active time
t
RAS
(max) 100
us
Row cycle time
@ Operating
t
RC(min)
60 63 ns 1
Last data in to col. address delay
t
CDL(min)
1 CLK
2
Last data in to row precharge
t
RDL(min)
2 CLK
2
Last data in to burst stop
t
BDL(min)
1 CLK
2
Output
870
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
30pF
Z0 =50
30pF
50
Vtt = 1.4V
3.3V
1200
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