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Datasheet: M12L64164A (No company)

1m X 16 Bit X 4 Banks Synchronous Dram

 

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ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
1/44
SDRAM
1M x 16 Bit x 4 Banks
Synchronous DRAM
FEATURES
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
15.6
s refresh interval
ORDERING INFORMATION

54 Pin TSOP (Type II)
(400mil x 875mil )
PRODUCT NO. MAX FREQ. PACKAGE Comments
M12L64164A-5TG
200MHz TSOP
II Pb-free
M12L64164A-6TG
166MHz TSOP
II
Pb-free
M12L64164A-7TG
143MHz TSOP
II Pb-free


GENERAL DESCRIPTION
The M12L64164A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by
16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
PIN ASSIGNMENT
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
DD
DQ0
V
DD Q
DQ1
DQ2
V
S S Q
DQ3
DQ4
V
DD Q
DQ5
DQ6
V
S S Q
DQ7
V
DD
LDQ M
W E
CAS
RAS
CS
A
13
A
12
A
10
/AP
A
0
A
1
A
2
A
3
V
DD
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
S S Q
DQ14
DQ13
V
DD Q
DQ12
DQ11
V
S S Q
DQ10
DQ9
V
DD Q
DQ8
V
SS
N C
U D Q M
CLK
CKE
N C
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
2/44
FUNCTIONAL BLOCK DIAGRAM















PIN FUNCTION DESCRIPTION
PIN NAME
INPUT
FUNCTION
CLK
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and L(U)DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
A0 ~ A11
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
A12 , A13
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column address on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ DQ15
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
VDD / VSS
Power Supply / Ground
Power and ground for the input buffers and the core logic.
VDDQ / VSSQ Data Output Power / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
NC
No Connection
This pin is recommended to be left No Connection on the device.
L(U)DQM
DQ
Mode
Register
Control Logic
Column
Address
Buffer
&
Refresh
Counter
Row
Address
Buffer
&
Refresh
Counter
Bank D
Row Decode
r
Bank A
Bank B
Bank C
Sense Amplifier
Column Decoder
Data Control Circuit
Latch Circuit
Input & Out
put
Buf
fer
Address
Clock
Generator
CLK
CKE
Command Deco
der
CS
RAS
CAS
WE
ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
3/44
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL
VALUE
UNIT
Voltage on any pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
, V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ +150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C
)
PARAMETER SYMBOL
MIN
TYP MAX
UNIT
NOTE
Supply voltage
V
DD
, V
DDQ
3.0 3.3
3.6
V
Input logic high voltage
V
IH
2.0 V
DD
+0.3 V
1
Input logic low voltage
V
IL
-0.3 0 0.8 V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
= -2mA
Output logic low voltage
V
OL
- - 0.4 V
I
OL
= 2mA
Input leakage current
I
IL
-5 - 5
A
3
Output leakage current
I
OL
-5 - 5
A
4
Note:
1. V
IH(max)
= 4.6V AC for pulse width
10ns acceptable.
2.
V
IL(min)
= -1.5V AC for pulse width
10ns acceptable.
3. Any input 0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.
D
out
is disabled , 0V
V
OUT
V
DD
.

CAPACITANCE
(VDD = 3.3V, TA = 25 C
, f = 1MHZ)
PARAMETER SYMBOL
MIN
MAX
UNIT
Input capacitance (A0 ~ A11, A13 ~ A12)
C
IN1
2 4 pF
Input capacitance
(CLK, CKE, CS , RAS , CAS , WE &
L(U)DQM)
C
IN2
2 4 pF
Data input/output capacitance (DQ0 ~ DQ15)
C
OUT
2 5 pF

ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
4/44

DC CHARACTERISTICS
Recommended operating condition unless otherwise notedTA = 0 to 70
C
VERSION
PARAMETER
SYMBOL
TEST CONDITION
-5 -6 -7
UNIT
NOTE
Operating Current
(One Bank Active)
I
CC1
Burst Length = 1, t
RC
t
RC(min)
, I
OL
= 0 mA,
tcc = tcc(min)
100 85 85 mA
1,2
I
CC2P
CKE
V
IL(max)
, tcc = tcc(min)
2
Precharge Standby Current
in power-down mode
I
CC2PS
CKE & CLK
V
IL(max)
, tcc =
1
mA
I
CC2N
CKE
V
IH(min)
, CS
V
IH(min)
, tcc = tcc(min)
Input signals are changed one time during 2CLK
20
Precharge Standby Current
in non power-down mode
I
CC2NS
CKE
V
IH(min)
, CLK
V
IL(max)
, tcc =
input signals are stable
10

mA
I
CC3P
CKE
V
IL(max)
, tcc = tcc(min)
10
Active Standby Current
in power-down mode
I
CC3PS
CKE & CLK
V
IL(max)
, tcc =
10
mA
I
CC3N
CKE
V
IH(min)
, CS
V
IH(min)
, tcc = tcc(min)
Input signals are changed one time during 2CLK
30 mA
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3NS
CKE
V
IH(min)
, CLK
V
IL(max)
, tcc =
input signals are stable
25 mA
Operating Current
(Burst Mode)
I
CC4
I
OL
= 0 mA, Page Burst, All Bank active
Burst Length = 4, CAS Latency = 3
180 150 140
mA 1,2
Refresh Current
I
CC5
t
RC
t
RC(min)
, t
CC
= tcc(min)
180 150 140
mA
Self Refresh Current
I
CC6
CKE
0.2V
1 mA
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
ESMT
M12L64164A
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2005
Revision: 2.6
5/44
AC OPERATING TEST CONDITIONS
(VDD = 3.3V 0.3V TA = 0 to 70 C
)
PARAMETER VALUE UNIT
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
VERSION
PARAMETER SYMBOL
-5 -6 -7
UNIT NOTE
Row active to row active delay
t
RRD(min)
10 12 14 ns
1
RAS to CAS delay
t
RCD(min)
15 18 20 ns
1
Row precharge time
t
RP(min)
15 18 20 ns
1
t
RAS(min)
38 40 42 ns
1
Row active time
t
RAS(max)
100 us
@ Operating
t
RC(min)
53 58 63 ns
1

Row cycle time
@ Auto refresh
t
RFC(min)
55 60 70 ns
1,5
Last data in to col. address delay
t
CDL(min)
1 CLK
2
Last data in to row precharge
t
RDL(min)
2 CLK
2
Last data in to burst stop
t
BDL(min)
1 CLK
2
Col. address to col. address delay
t
CCD(min)
1 CLK
3
CAS latency = 3
2
Number of valid
Output data
CAS latency = 2
1
ea 4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete with.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given t
RFC
after self refresh exit.
Output
870
V
OH
(DC) =2.4V , I
OH
= -2 mA
V
OL
(DC) =0.4V , I
OL
= 2 mA
Output
50pF
Z0 =50
50pF
50
Vtt = 1.4V
3.3V
1200
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