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Datasheet: M12L16161A-8T (No company)

512K x 16Bit x 2Banks Synchronous DRAM

 

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M12L16161A
Elite Semiconductor Memory Technology Inc.
P.1 Publication Date : Jan. 2000
Revision : 1.3u
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
z
JEDEC standard 3.3V power supply
z
LVTTL compatible with multiplexed address
z
Dual banks operation
z
MRS cycle with address key programs
-
CAS Latency (2 & 3 )
-
Burst Length (1, 2, 4, 8 & full page)
-
Burst Type (Sequential & Interleave)
z
All inputs are sampled at the positive going edge
of the system clock
z
Burst Read Single-bit Write operation
z
DQM for masking
z
Auto & self refresh
z
32ms refresh period (2K cycle)
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchro-
nous high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits, fabricated with
high performance CMOS technology. Synchro-
nous design allows precise cycle control with the
use of system clock I/O transactions are possible
on every clock cycle. Range of operating fre-
quencies, programmable burst length and pro-
grammable latencies allow the same device to be
useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
MAX Freq.
Interface
Package
M12L16161A-4.3T
233MHz
M12L16161A-5T
200MHz
M12L16161A-5.5T
183MHz
M12L16161A-6T
166MHz
M12L16161A-7T
143MHz
M12L16161A-8T
125MHz
LVTTL
50
TSOP(II)
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
M12L16161A
Elite Semiconductor Memory Technology Inc.
P.2 Publication Date : Jan. 2000
Revision : 1.3u
FUNCTIONAL BLOCK DIAGRAM
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
Address
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS
low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
L(U)DQM
Data Input / Output Mask
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ
0 ~ 15
Data Input / Output
Data inputs/outputs are multiplexed on the same pins.
V
DD
/V
SS
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Bank Select
Data Input Register
Column Decoder
Latency & Burst Length
Programming Register
512K x 16
512K x 16
Timing Register
Sens
e A
M
P
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
LDQM
LWCBR
DQi
LDQM
LWE
Co
l
.
B
u
f
f
e
r
LRAS
LC
B
R
LRAS
LCBR
LWE
LCAS
CLK
ADD
LCKE
O
u
t
put
B
u
ff
er
Ad
d
r
e
s
s
R
e
g
i
s
t
e
r
R
o
w
B
u
f
f
e
r
Ref
r
e
s
h
Count
e
r
R
o
w De
c
o
d
e
r
I/
O
C
o
nt
ro
l
M12L16161A
Elite Semiconductor Memory Technology Inc.
P.3 Publication Date : Jan. 2000
Revision : 1.3u
V
DDQ
/V
SSQ
Data Output Power/Ground
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
N.C/RFU
No Connection/
Reserved for Future Use
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
SS
V
IN,
V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
supply relative to V
SS
V
DD
,V
DDQ
-1.0 ~ 4.6
V
Storage temperature
T
STG
-55 ~ + 150
C
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
MA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70
C
)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
,V
DDQ
3.0
3.3
3.6
V
Input logic high voltage
V
IH
2.0
3.0
V
DD
+0.3
V
1
Input logic low voltage
V
IL
-0.3
0
0.8
V
2
Output logic high voltage
V
OH
2.4
-
-
V
I
OH
=-2mA
Output logic low voltage
V
OL
-
-
0.4
V
I
OL
= 2mA
Input leakage current
I
IL
-5
-
5
uA
3
Output leakage current
I
OL
-5
-
5
uA
4
Note : 1.V
IH
(max) = 4.6V AC for pulse width
10ns acceptable.
2.V
IL
(min) = -1.5V AC for pulse width
10ns acceptable.
3.Any input 0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V
V
OUT
V
DD
.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 25
C
, f = 1MHz)
Pin
Symbol
Min
Max
Unit
CLOCK
C
CLK
2.5
4.0
pF
RAS , CAS , WE , CS , CKE, LDQM,
UDQM
C
IN
2.5
5.0
pF
ADDRESS
C
ADD
2.5
5.0
pF
DQ0 ~DQ15
C
OUT
4.0
6.5
pF
M12L16161A
Elite Semiconductor Memory Technology Inc.
P.4 Publication Date : Jan. 2000
Revision : 1.3u
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
C
V
IH
(min)/V
IL
(max)=2.0V/0.8V)
Version
Parameter
Symbol
Test Condition
CAS
Latency -4.3 -5 -5.5 -6 -7 -8 Unit Note
Operating Current
(One Bank Active)
I
CC1
Burst Length = 1
t
RC
t
RC
(min),
t
CC
t
CC
(min), I
OL
= 0mA
250 230 210 190 160 140 mA 1
I
CC2
P
CKE
V
IL
(max),
t
CC
=15ns
2
mA
Precharge Standby
Current in power-down
mode
I
CC2
PS
CKE
V
IL
(max), CLK
V
IL
(max),
t
CC
=
2
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
30
mA
Precharge Standby
Current in non power-
down mode
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max),
t
CC
=
Input signals are stable
2
mA
I
CC3
P
CKE
V
IL
(max),
t
CC
=15ns
10
Active Standby Current
in power-down mode
I
CC3
PS
CKE
V
IL
(max), CLK
V
IL
(max),
t
CC
=
10
mA
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min),
t
CC
=15ns
Input signals are changed one time during 30ns
40
mA
Active Standby Current
in non power-down
mode
(One Bank Active)
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max),
t
CC
=
Input signals are stable
10
mA
3
270 250 230 210 180 160 mA
1
Operating Current
(Burst Mode)
I
CC
4
I
OL
= 0Ma, Page Burst
All Band Activated,
t
CCD
=
t
CCD
(min)
2
270 250 230 210 180 160
Refresh Current
I
CC
5
t
RC
t
RC
(min)
270 250 230 210 180 160 mA
2
Self Refresh Current
I
CC
6
CKE
0.2V
1
mA
Note: 1.Measured with outputs open. Addresses are changed only one time during
t
CC
(min).
2.Refresh period is 32ms. Addresses are changed only one time during
t
CC
(min).
M12L16161A
Elite Semiconductor Memory Technology Inc.
P.5 Publication Date : Jan. 2000
Revision : 1.3u
AC OPERATING TEST CONDITIONS
(V
DD
=3.3V
0.3V,T
A
= 0 to 70 C
)
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4 / 0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall time
tr / tf = 1 / 1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig.2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-4.3
-5
-5.5
-6
-7
-8
Unit
Note
Row active to row active delay
t
RRD
(min)
8.6
10
11
12
14
16
ns
1
RAS to CAS delay
t
RCD
(min)
12.9
15
16
16
16
20
ns
1
Row precharge time
t
RP
(min)
12.9
15
16
18
20
20
ns
1
t
RAS
(min)
34.4
40
40
42
42
48
ns
1
Row active time
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
47.3
55
60
60
63
68
ns
1
Last data in to new col. Address delay
t
CDL
(min)
1
CLK
2
Last data in to row precharge
t
RDL
(min)
1
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. Address to col. Address delay
t
CCD
(min)
1
CLK
3
CAS latency=3
1
Number of valid output data
CAS latency=2
1
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
4.
Minimum delay is required to complete write.
4.
All parts allow every cycle column address change.
4.
In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
3.3V
Output
(Fig.2) AC Output Load Circuit
30 pF
Vtt =1.4V
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
30 pF
Output
(Fig.1) DC Output Load circuit
Z0=50
870
1200
50
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