· Fast-settling, programmable, high-resolution PLL synthesizer
· Integrated power amplifier
· Analog and digital RSSI outputs
· Internal data filtering and clock recovery
· SPI compatible serial control interface
· Two 8 bit TX data registers
· Wake-up timer
· Low power consumption
· Toy controls
· Tire pressure monitoring
· Remote automatic meter reading
designed for use in applications requiring FCC or ETSI conformance for unlicensed
use in the 315, 433, 868 and 915 MHz bands. The IA4420 transceiver is a part of
is a complete analog RF and baseband transceiver including a multi-band PLL
synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and
amplifiers, and an I/Q demodulator. All required RF functions are integrated.
Only an external crystal and bypass filtering are needed for operation.
settling time allows for fast frequency-hopping, bypassing multipath fading and
interference to achieve robust wireless links. The PLL's high resolution allows the
usage of multiple channels in any of the bands. The receiver baseband bandwidth
(BW) is programmable to accommodate various deviation, data rate and crystal
tolerance requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external components (except crystal and
decoupling) are needed in most applications.
integrated digital data processing features: data filtering, clock recovery, data
pattern recognition, integrated FIFO and TX data register. The automatic frequency
control (AFC) feature allows the use of a low accuracy (low cost) crystal. To
minimize the system cost, the IA4420 can provide a clock signal for the
microcontroller, avoiding the need for two crystals.
on the internal wake-up timer.
XTL / REF
frequency bands at 315, 433, 868 and 915 MHz. The devices
facilitate compliance with FCC and ETSI requirements.
demodulation, allowing the use of a minimal number of external
components in a typical application. The IA4420 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna tuning,
an LNA with switchable gain, I/Q down converter mixers, baseband
filters and amplifiers, and an I/Q demodulator followed by a data
frequency, while preserving accuracy based on the on-chip crystal-
controlled reference oscillator. The PLL's high resolution allows the
usage of multiple channels in any of the bands.
only a few microseconds. Calibration always occurs when the
synthesizer starts. If temperature or supply voltage changes
significantly, VCO recalibration can be invoked easily. Recalibration
can be initiated at any time by switching the synthesizer off and
back on again.
can directly drive a loop antenna with a programmable output power
level. An automatic antenna tuning circuit is built in to avoid costly
trimming procedures and the so-called "hand effect."
(BW) of the baseband filters. This allows setting up the receiver
according to the characteristics of the signal to be received.
FSK deviation, data rate and crystal tolerance requirements. The
filter structure is 7th order Butterworth low-pass with 40 dB
suppression at 2*BW frequency. Offset cancellation is done by
using a high-pass filter with a cut-off frequency below 7 kHz.
the proposed antennas (see: Application Notes available from
external matching circuit is required to provide the correct matching
and to minimize the noise figure of the receiver.
highest gain) according to RF signal strength. It can be useful in an
environment with strong interferers.
using digital filtering according to the final application.
by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
integrated on the chip. An (external) capacitor can be chosen according
to the actual bit rate. In this mode, the receiver can handle up to 256
kbps data rate. The FIFO can not be used in this mode and clock is
not provided for the demodulated data.
29 times the bit rate. In this mode there is a clock recovery circuit
(CR), which can provide synchronized clock to the data. Using this
clock the received data can fill a FIFO. The CR has three operation
modes: fast, slow, and automatic. In slow mode, its noise immunity
is very high, but it has slower settling time and requires more accurate
data timing than in fast mode. In automatic mode the CR automatically
changes between fast and slow mode. The CR starts in fast mode,
then after locking it automatically switches to slow mode
clock. For analog operation, there is no need for setting the correct
a 10 MHz reference signal for the PLL. To reduce external parts and
simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal can
be found later in this datasheet.
so accurate timing is possible without the need for a second crystal.
band, center frequency of the synthesizer, and the bandwidth of the
baseband signal path. Division ratio for the microcontroller clock,
wake-up timer period, and low supply voltage detector threshold are
also programmable. Any of these auxiliary functions can be disabled
when not needed. All parameters are set to default after power-on;
the programmed values are retained during sleep mode. The interface
supports the read-out of a status register, providing detailed
information about the status of the transceiver and the received
It is possible to write 8 bits into the register in burst mode and the
internal bit rate generator transmits the bits out with the predefined
and read them out in a buffered mode.
the receiver can minimize the TX/RX offset in discrete steps, allowing
the use of:
goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available. The
RSSI settling time depends on the external filter capacitor. Pin 15 is
used as analog RSSI output. The digital RSSI can be can be monitored
by reading the status register.
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
and can be programmed from 1 ms to several days with an accuracy
at every 30 seconds. When the crystal oscillator is switched off, the
calibration circuit switches it back on only long enough for a quick
calibration (a few milliseconds) to facilitate accurate wake-up timing.
different power saving modes. Active mode can be initiated by several
wake-up events (negative logical pulse on nINT input, wake-up timer
timeout, low supply voltage detection, on-chip FIFO filled up or
receiving a request through the serial interface).
signal, which can be used to wake up the microcontroller, effectively
reducing the period the microcontroller has to be active. The source
of the interrupt can be read out from the transceiver by the
microcontroller through the SDO pin.
unfiltered received data. For correct operation, the "DQD threshold"
parameter must be filled in by using the Data Filter Command.
the appropriate bit using the Configuration Setting Command, the
chip provides a fixed number (196) of further clock pulses ("clock
tail") for the microcontroller to let it go to idle or sleep mode.
XTL / REF
In FIFO mode, when bit ef is set in Configuration Setting Command
el=0 in Configuration Setting Command
el=1 in Configuration Setting Command
ef=0 in Configuration Setting Command
ef=1 in Configuration Setting Command