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Datasheet: I90135 (No company)

Adsl Digital Chip

 

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Integrated Telecom Express, Inc.
1
I90135
Product Data Sheet
Version 1.2 (June 1999)
I90135-ADSL Digital Chip
Features
!
ANSI T1.413 Issue 2 standard DMT
modem with embedded, bypassable,
ATM framer
!
Byte interface or standard Utopia level 1
and level 2 ATM interfaces
!
Main functions include:
Receive Direction:
-
Rotor and adaptive frequency domain
equalizing
-
Demapping of DMT carriers into a
digital bitstream, including 4D trellis
coding
-
Error and noise monitoring on
individual carriers and pilot tones
-
Reed-Solomon decoding and
deinterleaving
-
ADSL deframing
-
ATM cell-specific deframing (can be
bypassed)
-
144-pin PQFP package
-
Power consumption 1 watt at 3.3V
Transmit Direction:
-
ATM cell-specific framing
-
ADSL framing
-
Reed-Solomon encoding
-
Mapping of digital bitstream onto DMT
carriers
-
Rotor and frequency domain gain
correction
General Description
ITeX's I90135 is the DMT modem and ATM
Framer of the Apollo series rate adaptive
ADSL chipset. The I90135 is intended to be
used in combination with I80134 analog
front end. In addition, the control function
of the chipset can be performed on a
dedicated external controller (see figure
1.1) or on host/control software eliminating
the need for a microcontroller (see figure
1.2).
The I90135 may be used in both ATU-C
(central office) and ATU-R (remote)
applications. The chip provides both a cell-
based UTOPIA level 1 and 2 ATM data
interface to the host and a non-ATM
synchronous bit stream.
The I90135 performs the DMT modulation,
demodulation, Reed-Solomon encoding, bit
interleaving, and 4D trellis coding.
The I90135 is in a 144-pin PQFP package.
Integrated Telecom Express, Inc.
2
I90135
Product Data Sheet
Version 1.2 (June 1999)
I90135
DMT Modem
and ATM Framer
I80134
Analog
Front End
POTS
Splitter
Line
I90188
PCI
Controller
Figure 1.2: General Block Diagram (Controllerless Configuration)
ADSL
Controller
Software
Host Based
A/B
Utopia
PCI
AFE
I90135
DMT Modem
and ATM Framer
I80134
Analog Front End
ATM
UTOPIA 1 & 2 interface
Hybrid
POTS
Splitter
Line
STM bitstream
Microprocessor or dedicated controller
FLASH
RAM
Figure 1.1: General Block Diagram
A/B
Integrated Telecom Express, Inc.
3
I90135
Product Data Sheet
Version 1.2 (June 1999)
Block Diagram
Introduction
The following essential describes the
sequence of actions for the receive
direction, corresponding functions for the
transmit direction are readily derived.
DSP Front End
The DSP front end contains four parts in
the receive direction: the input selector, the
analog front end interface, the decimator
and the time equalizer. The input selector
is used internally to enable test loopbacks
inside the chip. The analog front end
interface transfers 16-bit word, multiplexed
on four input/output signals. As a result,
four dock cycles are needed to transfer one
word. The decimator receives the 16-bit
samples at 8.8 MHz (as sent by the analog
front end chip) and reduces this rate to 2.2
MHz.
Test
Module
Data Symbol Timing Unit
VCXO
DSP
Front-end
FFT/
IFFT
Rotor
Trellis
Coding
Mapper/
Demapper
Generic
TC
Reed/
Solomon
ATM
Specific
TC
Reset
Controller Interface
Interface Module
Clock
Test Signals
AFE
Interface
SLAP
Utopia
Reset
Controller Bus
General Purpose I/Os
Figure 2: I90135 Block Diagram
Integrated Telecom Express, Inc.
4
I90135
Product Data Sheet
Version 1.2 (June 1999)
The Tme Equalizer (TEQ) module is an FIR
filter with programmable coefficients. Its
main purpose is to reduce the effect of
Inter-Symbol Interferences (ISI) by
shortening the channel impulse response.
Both the decimator and TEQ can be
bypassed.
In the transmit direction, the DSP front end
includes: sidelobe filtering, clipping, delay
equalization, and interpolation. The
sidelobe filtering and delay equalization are
implemented by IIR filters, reducing the
effect of echo in FDM systems.
Clipping is a statistical process limiting the
amplitude of the output signal, optimizing
the dynamic range of the AFE.
The interpolator receives data at 2.2 MHz
and generates samples at a rate of 8.8 MHz.
DMT Modem
This computational module is a
programmable DSP unit. Its instruction set
enables functions like FFT, IFFT, scaling,
rotor, and Frequency Equalization (FEQ).
This block implements the core of the DMT
algorithm as specified in ANSI T1.413.
In the RX path, the 51 2-point FFT
transforms the time domain DMT symbol
into a frequency domain representation,
which can be further decoded by the
subsequent demapping stages. After the
first stage time domain equalization and
FFT block an essentially ICI (InterCarrier
Interferences)-free carrier information
stream has been obtained. This stream is
still affected by carrier-specific channel
distortion resulting in an attenuation of the
signal amplitude and a rotation of the signal
phase. To compensate for these effects,
the FFT is followed by a Frequency Domain
Equalizer (FEQ) and a rotor (phase shifter).
In the TX path, the IFFT transforms the
DMT symbol generated in the frequency
domain by the mapper into a time domain
representation. The IFFT block is proceed
by a fne tune gain and a rotor stage,
allowing for a compensation of the possible
frequency mismatch between the master
clock frequency and the transmitter clock
frequency (which may be locked to another
reference). The FFT module is a slave DSP
engine controlled by the transceiver
controller. It works off line and
communicates with the other blocks via
buffers controlled by the DSTU block. The
DSP executes a program stored in a RAM
area, a very
flexible implementation open
for future enhancements.
DPLL
The Digital PLL module receives a metric for
the phase error of the pilot tone. In
general, the clock frequencies at the
transmitter and receiver do not match
exactly. The phase error is filtered and
integrated by a low pass filter, yielding an
estimation of the frequency offset. Various
processes can use this estimate to deal with
the frequency mismatch. In particular,
small accumulated phase error can be
compensated in the frequency domain by a
rotation of the received code constellation
(Rotor). Larger errors are compensated in
the time domain by inserting or deleting
clock cycles in the sample input sequence.
Integrated Telecom Express, Inc.
5
I90135
Product Data Sheet
Version 1.2 (June 1999)
Mapper/Demapper, Monitor, Trellis
Coding, FEQ Update
The demapper converts the constellation
points computed by the FFT to a block of
bits. This essentially consists in identifying
a point in a 2D QAM constellation plane.
The demapper supports trellis coded
demodulation and provides a Viterbi
maximum likelihood estimator. When the
trellis is active, the demapper receives an
indication for the most likely constellation
subset to be used. In the transmit
direction, the mapper performs the inverse
operation, mapping a block of bits into one
constellation point (in a complex x+jy
representation) which is passed to the IFFT
block. The Trellis Encoder generates
redundant bits to improve the robustness of
the transmission, using a 4-Dimensional
Trellis Coded Modulation scheme. The
Monitor computes error parameters for
carriers specified in the Demapper process.
Those parameters can be used for updates
of adaptive filters coefficient, clock phase
adjustments, error detection, etc. A series
of values is constantly monitored, such as
signal power, pilot phase deviations, symbol
erasures generation, loss of frame, etc.
Pin Diagram
VSS
1
AD_0
2
AD_1
3
AD_2
4
VDD
5
AD_3
6
AD_4
7
VSS
8
AD_5
9
AD_6
10
VDD
11
AD_7
12
AD_8
13
AD_9
14
VSS
15
AD_10
16
AD_11
17
VDD
18
AD_12
19
VSS
20
PCLK
21
VDD
22
AD_13
23
AD_14
24
AD_15
25
VSS
26
BE1
27
ALE
28
VDD
29
CSB
30
WR_RDB
31
RDYB
32
OBC_TYPE
33
INTB
34
RESETB
35
VSS
36
108
VDD
107
SLT_REQ_F
106
SLT_DAT_S0
105
SLT_DAT_S1
104
SLT_DAT_F0
103
SLT_DAT_F1
102
VSS
101 SLT_FRAME_F
100 SLAP_CLOCK
99
SLR_VAL_F
98
SLR_DAT_F0
97
SLR_DAT_F1
96
SLR_VAL_S
95
VDD
94
SLR_DAT_S0
93
SLR_DAT_S1
92 SLR_FRAME_S
91
VSS
90 SLR_FRAME_F
89 U_TX_ADDR_0
88 U_TX_ADDR_1
87 U_TX_ADDR_2
86
VDD
85 U_TX_ADDR_3
84 U_TX_ADDR_4
83
U_TX_DATA_0
82
U_TX_DATA_1
81
VDD
80
U_TX_DATA_2
79
U_TX_DATA_3
78
U_TX_DATA_4
77
U_TX_DATA_5
76
VDD
75
U_TX_DATA_6
74
U_TX_DATA_7
73
VSS
VD
D
1
4
4
A
FTX
D
_
3
1
4
3
A
FTX
D
_
2
1
4
2
VS
S
1
4
1
A
FTX
D
_
1
1
4
0
A
FTX
D
_
0
1
3
9
I
DDQ
13
8
VD
D
1
3
7
A
F
T
X
E
D
_3
13
6
A
F
T
X
E
D
_2
13
5
VS
S
1
3
4
A
F
T
X
E
D
_1
13
3
A
F
T
X
E
D
_0
13
2
VD
D
1
3
1
CT
RLD
A
T
A
13
0
M
C
LK
12
9
CL
WD
12
8
VS
S
1
2
7
A
F
RX
D_
3
1
2
6
A
F
RX
D_
2
1
2
5
A
F
RX
D_
1
1
2
4
A
F
RX
D_
0
1
2
3
VD
D
1
2
2
PD
O
W
N
1
2
1
GP
_OU
T
12
0
T
E
ST
SE
1
1
9
TR
S
T
B
1
1
8
VS
S
1
1
7
TC
K
1
1
6
VD
D
1
1
5
TMS
1
1
4
TD
O
1
1
3
TD
I
1
1
2
S
L
T_
FR
A
M
E
_
S
1
1
1
SL
T
_
R
E
Q
_
S
1
1
0
VS
S
1
0
9
37
V
D
D
38
U_
RX
DA
T
A
_
0
39
U_
RX
DA
T
A
_
1
40
V
S
S
41
U_
RX
DA
T
A
_
2
42
U_
RX
DA
T
A
_
3
43
V
D
D
44
U_
RX
DA
T
A
_
4
45
U_
RX
DA
T
A
_
5
46
V
S
S
47
U_
RX
DA
T
A
_
6
48
U_
RX
DA
T
A
_
7
49
V
D
D
50
U_
RX
_A
DDR
_0
51
U_
RX
_A
DDR
_1
52
U_
RX
_A
DDR
_2
53
U_
RX
_A
DDR
_3
54
V
S
S
55
U_
RX
_A
DDR
_4
56
GP
_I
N_
0
57
V
D
D
58
GP
_I
N_
1
59
V
S
S
60
U_
T
X
_RE
F
B
61
U_
RX
_R
E
F
B
62
V
D
D
63
U_
RX
CL
K
64
U_
RX
S
O
C
65
U_
RX
_C
LA
V
66
U_
RX
E
N
B
B
67
V
S
S
68
U_
T
X
CLK
69
U_
T
X
S
O
C
70
U_
T
X
_CL
A
V
7
1
U
_
T
X
EN
BB
72
V
D
D
AFE
TEST
SLAP
UTOPIA
OBC
Figure 3: Pinout (Topside View)
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