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Datasheet: M11S1644SA-60T (EliteMT (ESMT))

Org. = 4MbX4, Description = Edo 2.5V Self Refresh, Refresh = 2K, Speed/ Clock Freq...

 

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ESMT
M11S1644SA / M11D1644SA
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2001
Revision : 1.2 1/16
DRAM
4M x 4 DRAM
EDO PAGE MODE
FEATURES
!
x4
organization
!
EDO(Extended Data-Out) access mode
!
Single power supply :
2.5V
10% Vcc for S-ver product
2.0V
10% Vcc for D-ver product
!
LVTTL Interface for inputs and outputs
!
2048-cycle refresh in 32ms
!
Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN capabilities
!
Extended and Self-Refresh capabilities
!
Key AC Parameter
!
t
RAC
t
CAC
t
RC
t
PC
-50
50
13
84
20
-60
60
15
104
25
-80
80
20
134
35
-100
100
25
164
45
ORDERING INFORMATION - PACKAGE
JEDEC standard pinout :
24/26-pin 300mil SOJ
24/26-pin 300mil TSOP (TypeII)
PRODUCT NO.
Vcc
PACKING
TYPE
M11S1644SA-50J/60J/80J
2.5V
M11D1644SA-60J/80J/100J
2.0V
SOJ
M11S1644SA-50T/60T/80T
2.5V
M11D1644SA-60T/80T/100T
2.0V
TSOP
GENERAL DESCRIPTION
The M11S1644SA / M11D1644SA series is a randomly accessed solid state memory, organized as 4,194,304 x 4 bits device.
It offers Extended Data-Out access mode. Single power supply (2.5V
10%, 2.0V
10% ), access time (-50,-60,-80, -100) and
package type (SOJ, TSOPII) are optional features of this family. All these family have CAS - before - RAS , RAS -only refresh,
Hidden refresh, Extended and Self-Refresh capabilities.
The primary advantage of EDO is the availability of data-out even after CAS returns high. EDO allows CAS precharge
time (T
pc
) to occur without the output data going invalid. This elimination of CAS output control allows pipeline Read.
PIN ASSIGNMENT
SOJ Top View
TSOP (TypeII) Top View
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
2 4
2 3
22
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
V
C C
I/O0
I/O1
W E
RA S
N C
A10
A0
A1
A2
A3
V
C C
V
S S
I/O3
I/O2
CA S
OE
A9
A8
A7
A6
A5
A4
V
S S
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
V
CC
I/O0
I/O1
W E
RAS
N C
A10
A0
A1
A2
A3
V
CC
2 4
2 3
22
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
V
S S
I/O3
I/O2
CAS
OE
A9
A8
A7
A6
A5
A4
V
S S
ESMT
M11S1644SA / M11D1644SA
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2001
Revision : 1.2 2/16
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTIONS
PIN NO.
PIN NAME
TYPE
DESCRIPTION
8~11,14~19,7
A0~A10
Input
Address Input
Row Address : A0~A10
Column Address : A0~A10
5
RAS
Input
Row Address Strobe
21
CAS
Input
Column Address Strobe
4
WE
Input
Write Enable
20
OE
Input
Output Enable
2,3,22,23
I/O0 ~ I/O3
Input / Output
Data Input / Output
1,12
V
CC
Supply
Power, (2.5V or 2.0V)
13,24
V
SS
Ground
Ground
6
NC
-
No Connect
CONTROL
LOGIC
DATA-IN BUFFER
CLOCK
GENERATOR
DATA-OUT
BUFFER
COLUMN
ADDRESS
BUFFER
REFRESH
CONTROLER
REFRESH
COUNTER
ROW.
ADDRESS
BUFFERS(11)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
COLUMN
DECODER
OE
4


R
O
W
DE
CO
DE
R
2048 x 2048 x 4
MEMORY
ARRAY
4
SENSE AMPLIFIERS
I/O GATING
8
2048 x 4
V
CC
V
SS
IO0
:
IO3
RAS
2048
2048
11
11
11
11
CAS
V
BB
GENERATOR
WE
4
11
ESMT
M11S1644SA / M11D1644SA
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2001
Revision : 1.2 3/16
ABSOLUTE MAXIMUM RATINGS
Voltage on Any pin Relative to Vss ......-0.5V to V
CC
+0.5V
Operating Temperature, T
A
(ambient) ....0 C
to +70 C
Storage Temperature (plastic) ..........-55 C
to +150 C
Power Dissipation .......................................1.0W
Short Circuit Output Current ........................50Ma
Permanent device damage may occur if "Absolute
Maximum Ratings" are exceeded. This is a stress rating
only, and functional operation of the device above those
conditions indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0 C
T
A
70 C
, V
CC
= 2.5V
10% or V
CC
= 2.0V
10%)
2.5V
2.0V
PARAMETER
CONDITIONS
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
Supply Voltage
V
CC
2.25
2.75
1.8
2.2
V
1
Supply Voltage
V
SS
0
0
0
0
V
Input High Voltage
V
IH
1.8
V
CC
+0.2
1.4
V
CC
+0.2
V
1
Input Low Voltage
V
IL
-0.3
0.8
-0.3
0.6
V
1
Input Leakage Current
0V
V
IN
V
IH
(max)
I
LI
-5
5
-5
5
A
Output Leakage Current
0V
V
OUT
V
CC
+
0.2V
Output(s) disable
I
LO
-5
5
-5
5
A
Output High Voltage
I
OH
= -2 Ma
V
OH
2.0
-
1.4
-
V
Output Low Voltage
I
OL
= 2 Ma
V
OL
-
0.4
-
0.4
V
Note : 1.All Voltages referenced to V
SS
MAX
2.5V
2.0V
PARAMETER
CONDITIONS
SYMBOL
-50 -60 -80 -60 -80 -100
UNITS NOTES
Operating Current
RAS , CAS cycling , t
RC
=min
I
CC1
90
70
50
60
40
30
mA
1,2
TTL interface , RAS , CAS = V
IH
,
D
OUT
=High-Z
1.5 1.5 1.5 1.5 1.5 1.5
mA
Standby Current
CMOS interface,
RAS , CAS
V
CC
-0.2V
I
CC2
1
1
1
1
1
1
mA
RAS only refresh Current
t
RC
= min
I
CC3
90
70
50
60
40
30
mA
2
EDO Page Mode Current
t
PC
= min
I
CC4
90
70
50
60
40
30
mA
1,3
CAS Before RAS
Refresh Current
t
RC
= min
I
CC6
90
70
50
60
40
30
mA
Battery Backup Current
(S-ver. Only)
Standby with CBR refresh,
t
RC
=31.2us t
RAS
300ns,
D
OUT
=Hi-Z, CMOS interface
I
CC7
1
1
1
1
1
1
mA
Self Refresh Current
RAS , CAS
0.2V, D
OUT
=Hi-Z,
CMOS interface
I
CC8
1
1
1
1
1
1
mA
Note : 1. I
CC
max is specified at the output open condition.
2. Address can be changed twice or less while RAS =V
IL .
3. Address can be changed once or less while CAS =V
IH
.
ESMT
M11S1644SA / M11D1644SA
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2001
Revision : 1.2 4/16
CAPACITANCE
(Ta = 25 C
, V
CC
= 2.5V
10% or V
CC
= 2.0V
10% )
PARAMETER
SYMBOL
TYP
MAX
UNIT
Input Capacitance (address)
C
I1
-
5
pF
Input Capacitance ( RAS , CAS , WE , OE )
C
I2
-
7
pF
Output capacitance (I/O0~I/O3)
C
I / O
-
10
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70 C
, V
CC
= 2.5V
10% or V
CC
= 2.0
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : V
IL
=0.8V, V
IH
=1.8V (for 2.5V product), V
IL
=0.6V, V
IH
=1.4V (for 2.0V product)
Output reference level : V
OL
= 0.8V, V
OH
=1.6V (for 2.5V product), V
OL
= 0.6V, V
OH
=1.2V (for 2.0V product),
Output Load : 1TTL gate + CL (100pF)
Assumed t
T
= 2ns
-50
-60
-80
-100
UNIT Notes
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Read or Write Cycle Time
t
RC
84
104
134
164
ns
Read Write Cycle Time
t
RWC
110
135
180
225
ns
EDO-Page-Mode Read or Write
Cycle Time
t
PC
20
25
35
45
ns
EDO-Page-Mode Read-Write Cycle
Time
t
PCM
58
68
80
100
ns
Access Time From RAS
t
RAC
50
60
80
100
ns
4
Access Time From CAS
t
CAC
13
15
20
25
ns
5
Access Time From OE
t
OAC
13
15
20
25
ns
13
Access Time From Column Address
t
AA
25
30
40
50
ns
Access Time From CAS Precharge
t
ACP
28
33
45
60
ns
RAS Pulse Width
t
RAS
50
10,000
60
10,000
80
10,000
100
10,000
ns
RAS Pulse Width (EDO Page Mode)
t
RASC
50
100,000
60
100,000
80
100,000 100 100,000
ns
RAS Hold Time
t
RSH
7
10
10
15
ns
RAS Precharge Time
t
RP
30
40
50
60
ns
CAS Pulse Width
t
CAS
7
10,000
10
10,000
15
10,000
20
10,000
ns
18
CAS Hold Time
t
CSH
40
50
60
75
ns
CAS Precharge Time
t
CP
7
10
10
15
ns
6
RAS to CAS Delay Time
t
RCD
11
37
14
45
20
60
20
75
ns
7
CAS to RAS Precharge Time
t
CRP
5
5
5
10
ns
Row Address Setup Time
t
ASR
0
0
0
0
ns
Row Address Hold Time
t
RAH
7
10
10
15
ns
RAS to Column Address Delay Time
t
RAD
9
25
12
30
15
40
20
50
ns
8
Column Address Setup Time
t
ASC
0
0
0
0
ns
Column Address Hold Time
t
CAH
7
10
10
15
ns
Column Address Hold Time
(Reference to RAS )
t
AR
44
55
70
85
ns
Column Address to RAS Lead Time
t
RAL
25
30
40
50
ns
ESMT
M11S1644SA / M11D1644SA
Elite Semiconductor Memory Technology Inc.
Publication Date : Nov. 2001
Revision : 1.2 5/16
(Continued)
-50
-60
-80
-100
UNIT Notes
PARAMETER
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX
Read Command Setup Time
t
RCS
0
0
0
0
ns
15
Read Command Hold Time Reference to CAS
t
RCH
0
0
0
0
ns
9,15,
Read Command Hold Time Reference to RAS
t
RRH
0
0
0
0
ns
9
CAS to Output in Low-Z
t
CLZ
0
0
0
0
ns
Output Buffer Turn-off Delay From CAS or RAS
t
OFF1
0
13
0
15
0
20
0
25
ns
10,17
Output Buffer Turn-off to OE
t
OFF2
0
13
0
15
0
20
0
25
ns
17,19
Write Command Setup Time
t
WCS
0
0
0
0
ns 11,15,
Write Command Hold Time
t
WCH
7
10
10
15
ns
15
Write Command Hold Time(Reference to RAS )
t
WCR
44
55
70
85
ns
15
Write Command Pulse Width
t
WP
7
10
10
15
ns
15
Write Command to RAS Lead Time
t
RWL
13
15
20
25
ns
15
Write Command to CAS Lead Time
t
CWL
7
10
10
15
ns
15
Data-in Setup Time
t
DS
0
0
0
0
ns
12
Data-in Hold Time
t
DH
7
10
15
15
ns
12
Data-in Hold Time (Reference to RAS )
t
DHR
44
55
70
90
ns
RAS to WE Delay Time
t
RWD
67
79
107
135
ns
11
Column Address to WE Delay Time
t
AWD
42
49
67
85
ns
11
CAS to WE Delay Time
t
CWD
30
34
47
60
ns
11
Transition Time (rise or fall)
t
T
1
50
1
50
1
50
1
50
ns
2,3
Refresh Period (2048 cycles)
t
REF
32
32
32
32
ms
RAS to CAS Precharge Time
t
RPC
5
5
5
5
ns
CAS Setup Time(CBR REFRESH)
t
CSR
5
5
5
5
ns
1
CAS Hold Time(CBR REFRESH)
t
CHR
10
10
15
15
ns
1
OE Hold Time From WE During Read-Mode-Write
Cycle
t
OEH
7
10
20
20
ns
16
OE Low to CAS High Setup Time
t
OES
5
5
10
10
ns
OE High Hold Time From CAS High
t
OEHC
5
5
5
5
ns
OE Precharge Time
t
OEP
5
5
5
5
ns
OE Setup Prior to RAS During Hidden Refresh
Cycle
t
ORD
0
0
0
0
ns
Data Output Hold After CAS Returning Low
t
COH
3
3
3
3
ns
Output Disable Delay From WE
t
WHZ
0
13
0
15
0
20
0
25
ns
Self Refresh RAS Low Pulse width
t
RASS
100
100
100
100
us
20,21
Self Refresh RAS High Precharge Time
t
RPS
84
104
134
164
ns
20,21
Self Refresh CAS Hold Time
t
CHS
-50
-50
-50
-50
ns
20,21
Read Setup Time Reference to RAS in CBR/SR
t
RSR
0
0
0
0
ns
20,21
Read Hold Time Reference to RAS in CBR/SR
t
RHR
7
10
10
15
ns
20,21
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