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Datasheet: 7C1359A-150 (Cypress Semiconductor)

256K x 18 Synchronous-Pipelined Cache Tag RAM

 

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Cypress Semiconductor
256K x 18 Synchronous-Pipelined Cache Tag RAM
CY7C1359A/GVT71256T18
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-05120 Rev. **
Revised September 13, 2001
327
Features
Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
Fast clock speed: 166, 150, 133, and 100 MHz
Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
Pipelined data comparator
Data input register load control by DEN
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V 5% and +10% core power supply
2.5V or 3.3V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to V
SS
at all inputs and outputs
Common data inputs and data outputs
JTAG boundary scan
Byte Write Enable and Global Write control
Three chip enables for depth expansion and address
pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst se-
quence)
Automatic power-down for portable applications
Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE
2
and CE
2
), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE
2
, and CE
2
). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1DQ9. WEH controls DQ10DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
7C1359A-166
71256T36-6
7C1359A-150
71256T36-6.7
7C1359A-133
71256T36-7.5
7C1359A-100
71256T36-10
Maximum Access Time (ns)
3.5
3.8
4.0
4.5
Maximum Operating Current (mA)
310
275
250
190
Maximum CMOS Standby Current (mA)
20
20
20
20
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 2 of 24
Note:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Functional Block Diagram--256Kx18
[1]
D
Q
D
Q
WEH#
BWE#
WEL#
GW#
CE#
CE2
CE2#
HIGHER BYTE
WRITE
LOWER BYTE
WRITE
OUTPUT
REGISTER
OE#
hi byte write
ADSP#
ADSC#
Address
Register
Binary
Counter
& Logic
CLR
A
A1-A0
ADV#
MODE
256K x 9 x 2
S
RAM
Array
Output B
u
ffers
Input
Register
lo byte write
DQ1-
DQ18
D
Q
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
D
Q
Latch
DEN#
Compare
D
Q
MOE#
MATCH
CLK
Latch
16
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 3 of 24
Pin Configurations
100-Pin TQFP
Top View
A
NC
NC
V
CCQ
V
SSQ
NC
DQ9
DQ8
DQ7
V
SSQ
V
CCQ
DQ6
DQ5
V
SS
NC
V
CC
ZZ
DQ4
DQ3
V
CCQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
CCQ
MATCH
DEN
MOE
NC
NC
NC
V
CCQ
V
SSQ
NC
NC
DQ10
DQ11
V
SSQ
V
CCQ
DQ12
DQ13
V
CC
NC
V
SS
DQ14
DQ15
V
CCQ
V
SSQ
DQ16
DQ17
DQ18
NC
V
SSQ
V
CCQ
NC
NC
NC
A
A
CE
CE
2
NC
NC
WE
H
WE
L
CE
2
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1359A/GVT71256T18
NC
A
A
A
A
A1
A0
TM
S
TD
I
V
SS
V
CC
TD
O
TC
K
A
A
A
A
A
A
A
MO
D
E
1
2
3
4
5
6
7
A
V
CCQ
A
A
ADSP
A
A
V
CCQ
B
NC
CE
2
A
ADSC
A
CE
2
NC
C
NC
A
A
V
CC
A
A
NC
D
DQ10
NC
V
SS
NC
V
SS
DQ9
NC
E
NC
DQ11
V
SS
CE
V
SS
NC
DQ8
F
V
CCQ
NC
V
SS
OE
V
SS
DQ7
V
CCQ
G
NC
DQ12
WEH
ADV
V
SS
NC
DQ6
H
DQ13
NC
V
SS
GW
V
SS
DQ5
NC
J
V
CCQ
V
CC
NC
V
CC
NC
V
CC
V
CCQ
K
NC
DQ14
V
SS
CLK
V
SS
NC
DQ4
L
DQ15
NC
V
SS
NC
WEL
DQ3
NC
M
V
CCQ
DQ16
V
SS
BWE
V
SS
MATCH
V
CCQ
N
DQ17
NC
V
SS
A1
V
SS
DQ2
DEN
P
NC
DQ18
V
SS
A0
V
SS
MOE
DQ1
R
NC
A
MODE
V
CC
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
CCQ
TMS
TDI
TCK
TDO
NC
V
CCQ
119-Lead BGA
Top View
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 4 of 24
Pin Descriptions
BGA Pins
TQFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
A0
A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
5L
3G
93
94
WEL
WEH
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. WEL controls DQ1DQ9.
WEH controls DQ10DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit
WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip en-
ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock's rising edge.
4E
98
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
6B
92
CE
2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the
device.
2B
97
CE
2
input-
Synchronous
Chip Enable: This active HIGH input is used to enable the
device.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control
the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
4A
84
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
4B
85
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
3R
31
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
7T
64
ZZ
Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
7N
52
DEN
Input-
Synchronous
Data Input Enable: This active LOW input is used to control
the update of data input registers.
6M
53
MATCH
Output
Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 5 of 24
Notes:
2.
X means "don't care." H means logic HIGH. L means logic LOW. It is assumed in this table that ADSP is HIGH and ADSC is LOW.
3.
E=L is defined as CE=LOW and CE
2
=LOW and CE
2
=HIGH. E =H is defined as CE=HIGH or CE
2
=HIGH or CE
2
=LOW. WE is defined as [BWE + WEL*WEH]*GW.
4.
All inputs except OE and MOE must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5.
For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
6P
51
MOE
Input
Match Output Enable: This active LOW asynchronous input
enables the MATCH output drivers.
7P, 6N, 6L, 7K,
6H, 7G, 6F, 7E,
6D, 1D, 2E, 2G,
1H, 2K, 1L, 2M,
1N, 2P
58, 59, 62, 63, 68,
69, 72, 73, 74, 8,
9, 12, 13, 18, 19,
22, 23, 24
DQ1
DQ18
Input/
Output
Data Inputs/Outputs: Input data must meet setup and hold
times around the rising edge of CLK.
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output.
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
V
CC
Supply
Power Supply: +3.3V 5% and +10%
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
V
SS
Ground
Ground: GND
1A, 7A, 1F, 7F, 1J,
7J, 1M, 7M, 1U,
7U
4, 11, 20, 27, 54,
61, 70, 77
V
CCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to V
CC
)
1B, 7B, 1C, 7C,
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 2N, 1P, 1R,
5R, 7R, 1T, 4T, 6U
1-3, 6, 7, 14, 16,
25, 28-30, 56, 57,
66, 75, 78, 79, 95,
96
NC
-
No Connect: These signals are not internally connected.
Pin Descriptions
(continued)
BGA Pins
TQFP Pins
Name
Type
Description
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Partial Truth Table for MATCH
[2, 3, 4, 5, 6]
Operation
E
WE
DEN
MOE
OE
MATCH
DQ
READ Cycle
L
H
X
X
L
-
Q
WRITE Cycle
L
L
L
X
H
-
D
Fill WRITE Cycle
L
L
H
X
H
-
High-Z
COMPARE Cycle
L
H
L
L
H
Output
D
Deselected Cycle (MATCH Out)
H
X
X
L
X
H
High-Z
Deselected Cycle
H
X
X
H
X
High-Z
High-Z
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