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Datasheet: 5962-9736101QYA (Cypress Semiconductor)

16k/32k X 9 Deep Sync Fifos

 

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Cypress Semiconductor
16K/32K x 9 Deep Sync FIFOs
CY7C4261
CY7C4271
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-06015 Rev. *B
Revised August 21, 2003
Features
· High-speed, low-power, first-in first-out (FIFO)
memories
· 16K × 9 (CY7C4261)
· 32K × 9 (CY7C4271)
· 0.5-micron CMOS for optimum speed/power
· High-speed 100-MHz operation (10-ns read/write cycle
times)
· Low power -- I
CC
= 35 mA
· Fully asynchronous and simultaneous read and write
operation
· Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
· TTL-compatible
· Output Enable (OE
) pins
· Independent read and write enable pins
· Center power and ground pins for reduced noise
· Supports free-running 50% duty cycle clock inputs
· Width-Expansion Capability
· Military temp SMD Offering ­ CY7C4271-15LMB
· 32-pin PLCC/LCC and 32-pin TQFP
· Pin-compatible density upgrade to CY7C42X1 family
· Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
Functional Description
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
Logic Block Diagram
Pin Configuration
THREE-STATE
OUTPUT REGISTER
READ
CONTROL
FLAG
LOGIC
WRITE
CONTROL
WRITE
POINTER
READ
POINTER
RESET
LOGIC
INPUT
REGISTER
FLAG
PROGRAM
REGISTER
D
0
-
8
RCLK
EF
PAE
PAF
Q
0
-
8
WEN1
WCLK
RS
OE
RAM
ARRAY
16K x 9
32K x 9
WEN2/LD
REN1 REN2
FF
PLCC/LCC
D
1
D
0
RCLK
V
CC
D
8
D
7
D
6
D
5
D
4
D
3
GND
WCLK
WEN2/LD
Q
8
Q
7
D
2
D
8
D
7
D
6
D
5
D
4
D
3
D
2
PAF
PAE
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
REN1
OE
REN2
4 3 2 1
31 30
32
D
1
D
0
RCLK
GND
PAF
PAE
REN1
REN2
21
22
23
24
27
28
29
25
26
14 15 16 17 18 19 20
17
18
19
20
21
22
23
24
14 15 16
9 10 11 12 13
31 30
32
29 28 27
25
26
Q
6
Q
5
WEN1
RS
FF
Q
0
Q
1
Q
2
Q
3
Q
4
EF
FF
Q
0
Q
1
Q
2
Q
3
Q
4
EF
OE
V
CC
WCLK
WEN2/LD
Q
8
Q
7
Q
6
Q
5
WEN1
RS
TQFP
Top View
Top View
CY7C4261
CY7C4271
CY7C4261
CY7C4271
CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 2 of 18
Functional Description
(continued)
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full­7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
All configurations are fabricated using an advanced 0.5
µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Pin Definitions
Signal Name
Description
I/O
Description
D
0
-
8
Data Inputs
I
Data Inputs for 9-bit bus.
Q
0-
8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
Load
REN1, REN2
Read Enable
Inputs
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full
. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty
. When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO.
PAE is synchronized to RCLK.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO.
PAF is synchronized to WCLK.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state.
Selection Guide
7C4261/71-10
7C4261/71-15
7C4261/71-25
7C4261/71-35
Unit
Maximum Frequency
100
66.7
40
28.6
MHz
Maximum Access Time
8
10
15
20
ns
Minimum Cycle Time
10
15
25
35
ns
Minimum Data or Enable Set-up
3
4
6
7
ns
Minimum Data or Enable Hold
0.5
1
1
2
ns
Maximum Flag Delay
8
10
15
20
ns
Active Power Supply
Current (I
CC1
)
Commercial
35
35
35
35
mA
Industrial/
Military
40
40
40
40
CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 3 of 18
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q
0
-
8
) go LOW t
RSF
after the rising
edge of RS. In order for the FIFO to reset to its default state, a falling
edge must occur on RS and the user must not read or write while RS
is LOW. All flags are guaranteed to be valid t
RSF
after RS is taken
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH, and
FF is active HIGH, data present on the D
0
-
8
pins is written into the
FIFO on each rising edge of the WCLK signal. Similarly, when the
REN1 and REN2 signals are active LOW and EF is active HIGH, data
in the FIFO memory will be presented on the Q
0
-
8
outputs. New data
will be presented on each rising edge of RCLK while REN1 and
REN2 are active. REN1 and REN2 must set up t
ENS
before RCLK
for it to be a valid read function. WEN1 and WEN2 must occur t
ENS
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
0
-
8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q
0
-
8
outputs after t
OE
. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
0
-
8
outputs even
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for program-
mable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, WEN2/LD
can be used to access the four 8-bit offset registers contained in the
CY7C4261/71 for writing or reading data to these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and full
offset MSB register, respectively, when WEN2/LD and WEN1 are
LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD
and WEN1 are LOW writes data to the empty LSB register again.
Figure 1 shows the registers sizes and default values for the various
device types.
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) (PAF) states are deter-
mined by their corresponding offset registers and the
difference between the read and write pointers.
CY7C4261
CY7C4271
Density
16K × 9
32K × 9
Package
32-pin PLCC,TQFP
32-pin
LCC,PLCC,TQFP
Figure 1. Offset Register Location and Default Values
16K × 9
32K × 9
8
0
8
0
8
0
8
0
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
(MSB)
000000
(MSB)
000000
7
5
7
5
8
0
8
0
8
0
8
0
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
(MSB)
0000000
(MSB)
0000000
7
6
7
6
CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 4 of 18
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261 (16K-m) and CY7C4271
(32K-m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Width-Expansion Configuration
Word width may be increased simply by connecting the corre-
sponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and PAF)
can be detected from any one device. Figure 2 demonstrates
a 18-bit word width by using two CY7C4261/71s. Any word
width can be attained by adding additional CY7C4261/71s.
When the CY7C4261/71 is in a Width-Expansion Configu-
ration, the Read Enable (REN2) control input can be grounded
(see Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Flag Operation
The CY7C4261/71 devices provide four flag pins to indicate
the condition of the FIFO contents. Empty, Full, PAE, and PAF
are synchronous.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e.,
it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Note:
1.
The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2.
n = Empty Offset (n = 7 default value).
3.
m = Full Offset (m = 7 default value).
Table 1. Writing the Offset Registers
LD
WEN
WCLK
[1]
Selection
0
0
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Table 2. Status Flags
Number of Words in FIFO
FF
PAF
PAE
EF
CY7C4261
CY7C4271
0
0
H
H
L
L
1 to n
[2]
1 to n
[2]
H
H
L
H
(n+1) to (16384
-
(m+1))
(n+1) to (32768
-
(m+1))
H
H
H
H
(16384
-
m)
[3]
to 16383
(32768
-
m)
[3]
to 32767
H
L
H
H
16384
32768
L
L
H
H
CY7C4261
CY7C4271
Document #: 38-06015 Rev. *B
Page 5 of 18
Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration
FF
FF
EF
EF
WRITECLOCK (WCLK)
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
(WEN2/LD)
PROGRAMMABLE(PAF)
FULL FLAG (FF) # 1
CY7C4261/71
9
18
DATA IN (D)
RESET (RS)
9
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
9
DATA OUT (Q)
9
18
Read Enable 2 (REN2)
CY7C4261/71
EMPTY FLAG (EF) #2
FULL FLAG (FF) # 2
Read Enable 2 (REN2)
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