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Datasheet: 5962-90555023X (Cypress Semiconductor)

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Cypress Semiconductor

Document Outline

Reprogrammable Asynchronous
CMOS Logic Device
PLDC20RA10
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03012 Rev. **
Revised March 26, 1997
1PLDC20RA10
Features
Advanced-user programmable macrocell
CMOS EPROM technology for reprogrammability
Up to 20 input terms
10 programmable I/O macrocells
Output macrocell programmable as combinatorial or
asynchronous D-type registered output
Product-term control of register clock, reset and set and
output enable
Register preload and power-up reset
Four data product terms per output macrocell
Fast
-- Commercial
t
PD
= 15 ns
t
CO
= 15 ns
t
SU
= 7 ns
-- Military
t
PD
= 20 ns
t
CO
= 20 ns
t
SU
= 10 ns
Low power
-- I
CC
max - 80 mA (Commercial)
-- I
CC
max = 85 mA (Military)
High reliability
-- Proven EPROM technology
-- >2001V input protection
-- 100% programming and functional testing
Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PLDC20RA10 is a high-performance, sec-
ond-generation programmable logic device employing a flexi-
ble macrocell structure that allows any individual output to be
configured independently as a combinatorial output or as a
fully asynchronous D-type registered output.
The Cypress PLDC20RA10 provides lower-power operation
with superior speed performance than functionally equivalent
bipolar devices through the use of high-performance 0.8-mi-
cron CMOS manufacturing technology.
The PLDC20RA10 is packaged in a 24 pin 300-mil molded
DIP, a 300-mil windowed cerDIP, and a 28-lead square lead-
less chip carrier, providing up to 20 inputs and 10 outputs.
When the windowed device is exposed to UV light, the 20RA10
is erased and can then be reprogrammed.
Logic Block Diagram
4
9
8
7
6
5
4
3
2
1
10
15
16
17
18
19
20
21
22
23
24
I
I
I
I
I
I
I
I
4
4
4
4
4
4
4
V
CC
11
12
13
14
I
V
SS
OE
4
4
I
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
4
4
4
4
4
4
4
4
4
4
MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
9
8
7
6
5
4
3
2
1
0
PL
RA101
PLDC20RA10
Document #: 38-03012 Rev. **
Page 2 of 14
Macrocell Architecture
Figure 1 illustrates the architecture of the 20RA10 macrocell.
The cell dedicates three product terms for fully asynchronous
control of the register set, reset, and clock functions, as well
as, one term for control of the output enable function.
The output enable product term output is ANDed with the input
from pin 13 to allow either product term or hardwired external
control of the output or a combination of control from both
sources. If product-term-only control is selected, it is automat-
ically chosen for all outputs since, for this case, the external
output enable pin must be tied LOW. The active polarity of
each output may be programmed independently for each out-
put cell and is subsequently fixed. Figure 2 illustrates the out-
put enable options available.
When an I/O cell is configured as an output, combinatorial-only
capability may be selected by forcing the set and reset product
term outputs to be HIGH under all input conditions. This is
achieved by programming all input term programming cells for
these two product terms. Figure 3 illustrates the available out-
put configuration options.
An additional four uncommitted product terms are provided in
each output macrocell as resources for creation of user-de-
fined logic functions.
Programmable I/O
Because any of the ten I/O pins may be selected as an input,
the device input configuration programmed by the user may
vary from a total of nine programmable plus ten dedicated in-
puts (a total of nineteen inputs) and one output down to a
ten-input, ten-output configuration with all ten programmable
I/O cells configured as outputs. Each input pin available in a
given configuration is available as an input to the four control
product terms and four uncommitted product terms of each
programmable I/O macrocell that has been configured as an
output.
An I/O cell is programmed as an input by tying the output en-
able pin (pin 13) HIGH or by programming the output enable
product term to provide a LOW, thereby disabling the output
buffer, for all possible input combinations.
When utilizing the I/O macrocell as an output, the input path
functions as a feedback path allowing the output signal to be
fed back as an input to the product term array. When the output
cell is configured as a registered output, this feedback path
may be used to feed back the current output state to the device
inputs to provide current state control of the next output state
as required for state machine implementation.
Preload and Power-Up Reset
Functional testability of programmed devices is enhanced by
inclusion of register preload capability, which allows the state
of each register to be set by loading each register from an
external source prior to exercising the device. Testing of com-
plex state machine designs is simplified by the ability to load
an arbitrary state without cycling through long test vector se-
quences to reach the desired state. Recovery from illegal
states can be verified by loading illegal states and observing
recovery. Preload of a particular register is accomplished by
impressing the desired state on the register output pin and
lowering the signal level on the preload control pin (pin1) to a
logic LOW level. If the specified preload set-up, hold and pulse
width minimums have been observed, the desired state is
loaded into the register. To insure predictable system initializa-
tion, all registers are preset to a logic LOW state upon pow-
er-up, thereby setting the active LOW outputs to a logic HIGH.
Note:
1.
The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The
principal difference is in the location of the "no connect" (NC) pins
Selection Guide
Generic Part
Number
t
PD
ns
t
SU
ns
t
CO
ns
t
CC
ns
Com`l
Mil
Com'l
Mil
Com'l
Mil
Com'l
Mil
20RA10-15
15
7
15
80
20RA10-20
20
20
10
10
20
20
80
85
20RA10-25
25
15
25
85
20RA10-35
35
20
35
85
Pin Configurations
LCC
Top View
STD PLCC/HLCC
JEDEC PLCC/HLCC
Top View
Top View
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10
PLDC20RA10
NC
9
I
V
I/
O
I/
O
8
I/O
I/O
V
I
I
SS
V
I/
O
I/
O
0
1
0
1
CC
CC
9
8
I/O
I/O
V
I
I
SS
1
1
PL
RA102
RA103
RA104
I 0
1
I
I
I
I
I
I
2
3
4
5
6
7
8
9
OE
NC
NC
NC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
I/O
I/O
I/O
I/O
I/O
I/O
2
3
4
5
6
7
PLDC20RA10
I
I
V
I/O
I/O
0
1
CC
9
8
I/O
I/O
V SS
1
I3
I
I
4
5
NC
NC
I
6
OE
I
9
8
7
NC
PL
I
I 0
1
I 2
I
3
I
I
4
5
NC
I6
I7
I
I
9
8
NC
OE
NC
NC
I2
0
1
NC
PL
CG7C324
[1]
PLDC20RA10
Document #: 38-03012 Rev. **
Page 3 of 14
.
Figure 1. PLDC20RA10 Macrocell
PRELOAD
(FROM PIN 1)
OUTPUT ENABLE
(FROM PIN 13)
C0
R
S
P
Q
D
PL
1 S
O
TO I/O PIN
RA105
O
Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10
Programmable
OE
RA106
RA107
RA108
RA109
Output Always Enabled
External Pin
Combination of
Programmable and Hardwired
PLDC20RA10
Document #: 38-03012 Rev. **
Page 4 of 14
Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10
Registered/Active LOW
Combinatorial/Active LOW
Registered/Active HIGH
Combinatorial/Active HIGH
D
S
Q
R
D
S
Q
R
RA1010
RA1011
RA1012
RA1013
PLDC20RA10
Document #: 38-03012 Rev. **
Page 5 of 14
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. 65
C to +150
C
Ambient Temperature with
Power Applied............................................. 55
C to +125
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
DC Input Voltage......................................... 3.0 V to + 7.0 V
Output Current into Outputs (LOW) .............................16 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
DC Program Voltage .................................................... 13.0V
]
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +75
C
5V
10%
Military
[2]
55
C to +125
C
5V
10%
Electrical Characteristics
Over the Operating Range
[3]
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
V
IN
=V
IH
or V
IL
I
OH
= 3.2 mA
Com'l
2.4
V
I
OH
= 2 mA
Mil
V
OL
Output LOW Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OL
= 8 mA
0.5
V
V
IH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
[4]
2.0
V
V
IL
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
[4]
0.8
V
I
IX
Input Leakage Current
V
SS
V
IN
V
CC
, V
CC
= Max
10
+10
A
I
OZ
Output Leakage Current
V
CC
= Max., V
SS
V
OUT
V
CC
40
+40
A
I
SC
Output Short Circuit Current
[5]
V
CC
= Max., V
OUT
= 0.5V
[6]
30
90
mA
I
CC1
Standby Power Supply Current
V
CC
= Max., V
IN
= GND Outputs Open
Com'l
75
mA
Mil
80
mA
I
CC2
Power Supply Current at
Frequency
[5]
V
CC
= Max., Outputs Disabled (In High Z
State) Device Operating at f
MAX
Com'l
80
mA
Mil
85
mA
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 2.0 V @ f = 1 MHz
10
pF
C
OUT
Output Capacitance
V
OUT
= 2.0 V @ f = 1 MHz
10
pF
Notes:
2.
T
A
is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
4.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
5.
Tested initially and after any design or process changes that may affect these parameters.
6.
Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5 V has been chosen to
avoid test problems caused by tester ground degradation.
PLDC20RA10
Document #: 38-03012 Rev. **
Page 6 of 14
AC Test Loads and Waveforms (Commercial)
RA1014
RA1015
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
< 5 ns
< 5 ns
OUTPUT
R1 457
(470
MIL)
R2
270
(319
Mil)
170
Equivalent to:
TH VENIN EQUIVALENT(Commercial)
1.86V=V
thc
R1 457
(470
MIL)
R2
270
(319
Mil)
OUTPUT
190
Equivalent to:
TH VENIN EQUIVALENT(Military)
2.02V=V
thc
RA1016
RA1017
Parameter
V
th
Output Waveform Measurement Level
t
PXZ( )
1.5V
V
OH
0.5V
V
X
0.5V
t
PXZ(+)
2.6V
V
OL
V
X
t
PZX(+)
V
thc
0.5V
t
PZX( )
V
thc
V
OL
0.5V
V
X
V
OH
RA1018
RA1019
RA1020
RA1021
V
X
0.5V
V
X
RA1022
V
OH
0.5V
V
OL
V
X
0.5V
V
X
V
OH
RA1023
RA1024
0.5V
V
OL
RA1025
V
X
t
ER()
t
ER(+)
t
EA(+)
t
EA( )
1.5V
2.6V
V
thc
V
thc
(c)
PLDC20RA10
Document #: 38-03012 Rev. **
Page 7 of 14
Switching Characteristics
Over the Operating Range
[3, 7, 8]
Parameter
Description
Commercial
Military
Unit
15
20
20
25
35
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
t
PD
Input or Feedback to
Non-Registered Output
15
20
20
25
35
ns
t
EA
Input to Output Enable
15
20
20
30
35
ns
t
ER
Input to Output
Disable
15
20
20
30
35
ns
t
PZX
Pin 13 to Output
Enable
12
15
15
20
25
ns
t
PXZ
Pin 13 to Output
Disable
12
15
15
20
25
ns
t
CO
Clock to Output
15
20
20
25
35
ns
t
SU
Input or Feedback
Set-Up Time
7
10
10
15
20
ns
t
H
Hold Time
3
5
3
5
5
ns
t
P
Clock Period
(t
SU
+ t
CO)
22
30
30
40
55
ns
t
WH
Clock Width HIGH
[5]
10
13
12
18
25
ns
t
WL
Clock Width LOW
[5]
10
13
12
18
25
ns
f
MAX
Maximum Frequency
(1/t
P
)
[5]
45.5
33.3
33.3
25.0
18.1
MHz
t
S
Input of Asynchronous
Set to Registered Output
15
20
20
25
40
ns
t
R
Input of Asynchronous
Reset to Registered
Output
15
20
20
25
40
ns
t
ARW
Asynchronous Reset
Width
[5]
15
20
20
25
25
ns
t
ASW
Asynchronous S-Width
[5]
15
20
20
25
25
ns
t
AR
Asynchronous Set/
Reset Recovery Time
10
12
12
15
20
ns
t
WP
Preload Pulse Width
15
15
15
15
15
ns
t
SUP
Preload Set-Up Time
15
15
15
15
15
ns
t
HP
Preload Hold Time
15
15
15
15
15
ns
Notes:
7.
Part (a) of AC Test Loads was used for all parameters except t
EA
, t
ER
, t
PZX
and t
PXZ
, which use part (b).
8.
The parameters t
ER
and t
PXZ
are measured as the delay from the input disable logic threshold transition to V
OH
- 0.5 V for an enabled HIGH output or V
OL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
PLDC20RA10
Document #: 38-03012 Rev. **
Page 8 of 14
Switching Waveform
CP
RESET
ASYNCHRONOUS
ASYNCHRONOUS
OUTPUTS
(HIGHASSERTED)
SET
OUTPUT ENABLE
INPUTPIN
INPUTS,REGISTERED
FEEDBACK
t
AR
t
PD
t
CO
t
WH
t
WL
t
SU
t
ER
t
EA
t
P
RA1026
t
H
Preload Switching Waveform
Asynchronous Reset
Asynchronous Set
t
EA
t
ER
t
HP
t
SUP
t
WP
RA1027
PIN 13
OUTPUT
ENABLE
REGISTER
OUTPUTS
PIN 1
PRELOAD
CLOCK
RA1028
t
R
t
ARW
ASYNCHRONOUS
RESET
OUTPUT
RA1029
t
S
t
ASW
ASYNCHRONOUS
SET
OUTPUT
PLDC20RA10
Document #: 38-03012 Rev. **
Page 9 of 14
Functional Logic Diagram
PLDC20RA10
Document #: 38-03012 Rev. **
Page 10 of 14
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
I
CC2
t
PD
(ns)
t
SU
(ns)
t
CO
(ns)
Ordering Code
Package
Name
Package Type
Operating
Range
80
15
7
15
PLDC20RA10-15JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
PLDC20RA10-15PC
P13
24-Lead (300-Mil) Molded DIP
CG7C324-A15JC
J64
28-Lead Plastic Leaded Chip Carrier
20
10
20
PLDC20RA10-20PC
P13
24-Lead (300-Mil) Molded DIP
CG7C324-A20JC
J64
28-Lead Plastic Leaded Chip Carrier
85
20
10
20
PLDC20RA10-20DMB
D14
24-Lead (300-Mil) CerDIP
Military
PLDC20RA10-20WMB
W14
24-Lead (300-Mil) Windowed CerDIP
25
15
25
PLDC20RA10-25DMB
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10-25WMB
W14
24-Lead (300-Mil) Windowed CerDIP
35
20
35
PLDC20RA10-35DMB
D14
24-Lead (300-Mil) CerDIP
PLDC20RA10-35WMB
W14
24-Lead (300-Mil) Windowed CerDIP
DC Characteristics
Parameter
Subgroups
V
OH
1, 2, 3
V
OL
1, 2, 3
V
IH
1, 2, 3
V
IL
1, 2, 3
I
IX
1, 2, 3
I
OZ
1, 2, 3
I
CC
1, 2, 3
Switching Characteristics
Parameter
Subgroups
t
PD
9, 10, 11
t
PZX
9, 10, 11
t
CO
9, 10, 11
t
SU
9, 10, 11
t
H
9, 10, 11
DC Characteristics
Parameter
Subgroups
PLDC20RA10
Document #: 38-03012 Rev. **
Page 11 of 14
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835
D- 9Config.A
28-Lead Plastic Leaded Chip Carrier J64
28-Square
Leadless
Chip
Carrier
L64
MIL-STD-1835 C-4
28-Pin Windowed Leadless Chip Carrier Q64
MIL-STD-1835 C-4
PLDC20RA10
Document #: 38-03012 Rev. **
Page 12 of 14
Package Diagrams
(continued)
28-Pin Windowed Leaded Chip Carrier H64
PLDC20RA10
Document #: 38-03012 Rev. **
Page 13 of 14
Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams
(continued)
24-Lead (300-Mil) Molded DIP P13/P13A
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835
D- 9 Config.A
PLDC20RA10
Document #: 38-03012 Rev. **
Page 14 of 14
Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device
Document Number: 38-03012
REV.
ECN NO.
Issue Date
Orig. of Change
Description of Change
**
106294
04/24/01
SZV
Change from Spec number: 38-00073 to 38-03012
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