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Datasheet: 5962-88735033X (Cypress Semiconductor)

 

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Cypress Semiconductor
2K x 8 Reprogrammable Registered PROM
CY7C245A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-04007 Rev. *B
Revised December 27, 2002
1CY7C245A
Features
Windowed for reprogrammability
CMOS for optimum speed/power
High speed
-- 15-ns address set-up
-- 10-ns clock to output
Low power
-- 330 mW (commercial) for -25 ns
-- 660 mW (military)
Programmable synchronous or asynchronous output
enable
On-chip edge-triggered registers
Programmable asynchronous register (INIT)
EPROM technology, 100% programmable
Slim, 300-mil, 24-pin plastic or hermetic DIP
5V
10% V
CC
, commercial and military
TTL-compatible I/O
Direct replacement for bipolar PROMs
Capable of withstanding greater than 2001V static
discharge
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
The CY7C245A replaces bipolar devices and offers the advan-
tages of lower power, reprogrammability, superior perfor-
mance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram
PinConfigurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
8
A
9
INIT
CP
O
7
O
6
O
4
O
5
O
3
PROGRAMMABLE
ARRAY
MULTIPLEXER
15
8-BIT
EDGE-
REGISTER
TRIGGERED
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
CP
CP
E/E
S
E/E
S
28
4
5
6
7
8
9
10
3 2 1
27
1314151617
26
25
24
23
22
21
20
11
12
19
A 5
V CC
GND
A 6 A 7
O
3
O
1
O
0
18
O
4
O
5
NC
A
0
A
4
A
3
A
10
NC
NC
NC
INIT
E/E
S
O
7
O
6
A
2
A
1
CP
O
2
A 8
INIT
INIT
IA
L
I
Z
E
W
O
RD
PR
O
G
RA
M
M
A
B
L
E
A 9
PROGRAMMABLE
MULTIPLEXER
D
Q
C
A
10
ADDRESS
DECODER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
8
A
9
A
10
A
7
COLUMN
ADDRESS
ROW
ADDRESS
DIP
Top View
LCC/PLCC (Opaque only)
Top View
Selection Guide
7C245A-15
7C245A-18
7C245A-25
7C245A-35
Unit
Minimum Address Set-Up Time
15
18
25
35
ns
Maximum Clock to Output
10
12
12
15
ns
Maximum Operating
Current
Standard
Commercial
120
120
90
90
mA
Military
120
120
120
mA
CY7C245A
Document #: 38-04007 Rev. *B
Page 2 of 11
Maximum Ratings
[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
.....................................-
65
C to +150
C
Ambient Temperature with
Power Applied
..................................................-
55
C to +125
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)
.................................................-
0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
.....................................................-
0.5V to +7.0V
DC Input Voltage
.................................................-
3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
UV Erasure................................................... 7258 Wsec/cm
2
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
]
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +70
C
5V
10%
Military
[2]
-
55
C to +125
C
5V
10%
Electrical Characteristics
Over the Operating Range
[3,4]
7C245A-15
7C245A-18
7C245A-25
7C245A-35
7C245A-45
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
Unit
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
=
-
4.0 mA
V
IN
= V
IH
or V
IL
2.4
2.4
2.4
V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 16 mA
V
IN
= V
IH
or V
IL
0.4
0.4
0.4
V
V
IH
Input HIGH Level
Guaranteed Input Logical
HIGH Voltage for All Inputs
2.0
V
CC
2.0
V
CC
2.0
V
CC
V
V
IL
Input LOW Level
Guaranteed Input Logical
LOW Voltage for All Inputs
0.8
0.8
0.8
V
I
IX
Input Leakage Current GND < V
IN
< V
CC
-
10
+10
-
10
+10
-
10
+10
A
V
CD
Input Clamp Diode
Voltage
Note 4
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
Output Disabled
[5]
-
10
+10
-
10
+10
-
10
+10
A
I
OS
Output Short
Circuit Current
V
CC
= Max.,
V
OUT
= 0.0V
[6]
-
20
-
90
-
20
-
90
-
20
-
90
mA
I
CC
Power Supply Current V
CC
= Max.,
I
OUT
= 0 mA
Com'l
120
120
90
mA
Mil
120
120
V
PP
Programming Supply
Voltage
12
13
12
13
12
13
V
I
PP
Programming Supply
Current
50
50
50
mA
V
IHP
Input HIGH
Programming Voltage
3.0
3.0
3.0
V
V
ILP
Input LOW
Programming Voltage
0.4
0.4
0.4
V
Capacitance
[4]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
C, f = 1 MHz,
V
CC
= 5.0V
10
pF
C
OUT
Output Capacitance
10
pF
Notes:
1.
The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2.
T
A
is the "instant on" case temperature.
3.
See the last page of this specification for Group A subgroup testing information.
4.
See the "Introduction to CMOS PROMs" section of the Cypress Data Book for general information on testing.
5.
For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
CY7C245A
Document #: 38-04007 Rev. *B
Page 3 of 11
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (E
S
) or
asynchronous (E) output enable and asynchronous initialization
(INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (E
S
or E). If the
synchronous enable (E
S
) has been programmed, the register will be
in the set condition causing the outputs (O
0
O
7
) to be in the OFF or
high-impedance state. If the asynchronous enable (E) is being used,
the outputs will come up in the OFF or high-impedance state only if
the enable (E) input is at a HIGH logic level. Data is read by applying
the memory location to the address inputs (A
0
A
10
) and a logic LOW
to the enable input. The stored data is accessed and loaded into the
master flip-flops of the data register during the address set-up time.
At the next LOW-to-HIGH transition of the clock (CP), data is trans-
ferred to the slave flip-flops, which drive the output buffers, and the
accessed data will appear at the outputs (O
0
O
7
).
If the asynchronous enable (E) is being used, the outputs may be
disabled at any time by switching the enable to a logic HIGH, and may
be returned to the active state by switching the enable to a logic LOW.
If the synchronous enable (E
S
) is being used, the outputs will go
to the OFF or high-impedance state upon the next positive clock edge
after the synchronous enable input is switched to a HIGH level. If the
synchronous enable pin is switched to a logic LOW, the subsequent
positive clock edge will return the output to the active state. Following
a positive clock edge, the address and synchronous enable inputs
are free to change since no change in the output will occur until the
next LOW-to-HIGH transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the next
location while previously addressed data remains stable on
the outputs.
AC Test Loads and Waveforms
[3, 4]
3.0V
5V
OUTPUT
R1 250
R2
167
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
5 ns
5 ns
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b) HighZ Load
OUTPUT
2.0V
Equivalent to: TH VENIN EQUIVALENT
100
R1 250
(a) Normal Load
R2
167
ALL INPUT PULSES
Switching Characteristics
Over Operating Range
[3, 4]
7C245A-15 7C245A-18
7C245A-35
7C245A-25
7C245A-35
Parameter
Description
Min. Max. Min. Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
t
SA
Address Set-Up to Clock HIGH
15
18
25
35
45
ns
t
HA
Address Hold from Clock HIGH
0
0
0
0
0
ns
t
CO
Clock HIGH to Valid Output
10
12
12
15
25
ns
t
PWC
Clock Pulse Width
10
12
15
20
20
ns
t
SES
E
S
Set-Up to Clock HIGH
10
10
12
15
15
ns
t
HES
E
S
Hold from Clock HIGH
5
5
5
5
5
ns
t
DI
Delay from INIT to Valid Output
15
20
20
20
35
ns
t
RI
INIT Recovery to Clock HIGH
10
12
15
20
20
ns
t
PWI
INIT Pulse Width
10
12
15
20
25
ns
t
COS
Valid Output from Clock HIGH
[7]
15
15
15
20
30
ns
t
HZC
Inactive Output from Clock
HIGH
[7]
15
15
15
20
30
ns
t
DOE
Valid Output from E LOW
[8]
12
15
15
20
30
ns
t
HZE
Inactive Output from E HIGH
[8]
15
15
15
20
30
ns
Notes:
7.
Applies only when the synchronous (E
S
) function is used.
8.
Applies only when the asynchronous (E) function is used.
CY7C245A
Document #: 38-04007 Rev. *B
Page 4 of 11
Operating Modes
(Continued)
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophisticated
functions such as a built-in "jump start" address. When activated, the
initialize control input causes the contents of a user-programmed
2049th 8-bit word to be loaded into the on-chip register. Each bit is
programmable and the initialize function can be used to load any
desired combination of 1s and 0s into the register. In the unpro-
grammed state, activating INIT will generate a register CLEAR (all
outputs LOW). If all the bits of the initialize word are programmed,
activating INIT performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load of the
programmed initialize word into the master and slave flip-flops of the
register, independent of all other inputs, including the clock (CP). The
initialize data will appear at the device outputs after the outputs are
enabled by bringing the asynchronous enable (E) LOW.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm
2
power rating the exposure time
would be approximately 35 minutes. The 7C245A needs to be within
1 inch of the lamp during erasure. Permanent damage may result if
the PROM is exposed to high-intensity UV light for an extended
period of time. 7258 Wsec/cm
2
is the recommended maximum
dosage.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Control Byte
00 ............ Asynchronous output enable (default state)
01 .....................................Synchronous output enable
Switching Waveforms
[4]
t
DI
t
CO
t
DOE
t
HZE
t
HZC
t
SA
t
HA
t
HES
t
SES
C245A-7
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
t
PWC
t
HA
t
CO
t
COS
O
0
-
O
7
A
0
-
A
10
INIT
CP
E
S
E
t
RI
t
PWI
t
HES
t
SES
t
HES
t
SES
Bit Map Data
Programmer Address
RAM Data
Decimal
Hex
Contents
0
0
Data
.
.
.
.
.
.
.
.
.
2047
7FF
Data
2048
800
Init Byte
2049
801
Control Byte
CY7C245A
Document #: 38-04007 Rev. *B
Page 5 of 11
Table 1. Mode Selection
Pin Function
[9]
Read or Output Disable
A
10
A
4
A
3
A
2
A
1
A
0
CP
E, E
S
INIT
O
7
O
0
Mode
Other
A
10
A
4
A
3
A
2
A
1
A
0
PGM
VFY
V
PP
D
7
D
0
Read
A
10
A
4
A
3
A
2
A
1
A
0
V
IL
/V
IH
V
IL
V
IH
O
7
O
0
Output Disable
A
10
A
4
A
3
A
2
A
1
A
0
X
V
IH
V
IH
High Z
Initialize
A
10
A
4
A
3
A
2
A
1
A
0
X
V
IL
V
IL
Init. Byte
Program
A
10
A
4
A
3
A
2
A
1
A
0
V
ILP
V
IHP
V
PP
D
7
D
0
Program Verify
A
10
A
4
A
3
A
2
A
1
A
0
V
IHP
V
ILP
V
PP
O
7
O
0
Program Inhibit
A
10
A
4
A
3
A
2
A
1
A
0
V
IHP
V
IHP
V
PP
High Z
Intelligent Program
A
10
A
4
A
3
A
2
A
1
A
0
V
ILP
V
IHP
V
PP
D
7
D
0
Program Synchronous Enable
A
10
A
4
V
IHP
A
2
A
1
V
PP
V
ILP
V
IHP
V
PP
High Z
Program Initialization Byte
A
10
A
4
V
ILP
A
2
A
1
V
PP
V
ILP
V
IHP
V
PP
D
7
D
0
Blank Check Zeros
A
10
A
4
A
3
A
2
A
1
A
0
V
IHP
V
ILP
V
PP
Zeros
Note:
9.
X = "don't care" but not to exceed V
CC
+5%.
Figure 1. Programming Pinouts
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
V
CC
D
7
D
6
D
4
D
5
D
3
15
A
9
A
10
V
PP
VFY
PGM
28
4
5
6
7
8
9
10
3 2 1
27
1314151617
26
25
24
23
22
21
20
11
12
19
A
5
V CC
GN
D
A
6
A
7
D
3
D
1
D
0
18
D
4
D
5
NC
A
0
A
4
A
3
A
8
NC
NC
D
7
D
6
A
2
A
1
D
2
A
10
V
PP
VFY
PGM
NC
A
9
DIP
LCC/PLCC (Opaque Only)
Top View
Top View
CY7C245A
Document #: 38-04007 Rev. *B
Page 6 of 11
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0
4.5
5.0
5.5
6.0
-
55
25
125
1.2
1.1
1.6
4.0
4.5
5.0
5.5
6.0
NORMA
L
I
Z
E
D
CLOCK
-
T
O
-OUT
P
U
T

T
I
ME
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
C)
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. V
CC
0.6
1.2
1.6
1.4
1.2
1.0
0.8
-
55
125
NORM
A
L
IZ
E
D
S
E
T
-
UP

T
I
M
E
AMBIENT TEMPERATURE (
C)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
150
175
125
75
50
25
0.0
1.0
2.0
3.0
OUT
P
UT
S
I
N
K
C
URRE
NT

(mA
)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
NORM
A
L
IZ
E
D
I
CC
NORM
A
L
IZ
E
D
I
CC
V
CC
=5.0V
T
A
=25
C
T
A
=25
C
0.6
0.6
1.02
1.00
0.98
0.96
0.94
0.92
0
25
50
75
CLOCK PERIOD (ns)
30.0
25.0
20.0
15.0
10.0
5.0
0
200
400
600
800
DEL
T
A
t
(
n
s
)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
100
0.0
1000
T
A
=25
C
V
CC
=4.5V
T
A
=25
C
f = f
MAX
25
0.88
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
4.0
1.4
1.2
1.0
0.8
1.6
1.4
1.2
1.0
0.8
-
55
125
NORM
A
L
IZ
E
D
S
E
T
-
UP

T
I
M
E
0.6
25
AMBIENT TEMPERATURE (
C)
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.2
4.0
4.5
5.0
5.5
6.0
NORMA
L
I
Z
E
D
CL
OCK
-
T
O
-OUT
P
U
T

T
I
M
E
0.4
SUPPLY VOLTAGE (V)
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
T
A
=25
C
1.0
0.8
0.6
NORM
A
L
IZ
ED I
CC
0.90
V
CC
=5.5V
T
A
=25
C
CY7C245A
Document #: 38-04007 Rev. *B
Page 7 of 11
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Ordering Information
Speed (ns)
I
CC
(mA)
Ordering
Code
Package
Type
Package Type
Operating
Range
t
SA
t
CO
15
10
120
CY7C245A-15JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
18
12
120
CY7C245A-18JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
CY7C245A-18PC
P13
24-Lead (300-Mil) Molded DIP
CY7C245A-18WC
W14
24-Lead (300-Mil) Windowed CerDIP
18
12
120
CY7C245A-18DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C245A-18QMB
Q64
28-Pin Windowed Leadless Chip Carrier
CY7C245A-18WMB
W14
24-Lead (300-Mil) Windowed CerDIP
25
15
60
CY7C245A-25PC
P13
24-Lead (300-Mil) Molded DIP
Commercial
CY7C245A-25WC
W14
24-Lead (300-Mil) Windowed CerDIP
90
CY7C245A-25JC
J64
28-Lead Plastic Leaded Chip Carrier
CY7C245A-25SC
S13
24-Lead Molded SOIC
35
20
60
CY7C245A-35WC
W14
24-Lead (300-Mil) Windowed CerDIP
Commercial
90
CY7C245A-35JC
J64
28-Lead Plastic Leaded Chip Carrier
120
CY7C245A-35DMB
D14
24-Lead (300-Mil) CerDIP
Military
CY7C245A-35QMB
Q64
28-Pin Windowed Leadless Chip Carrier
DC Characteristics
Parameter
Subgroups
V
OH
1, 2, 3
V
OL
1, 2, 3
V
IH
1, 2, 3
V
IL
1, 2, 3
I
IX
1, 2, 3
I
OZ
1, 2, 3
I
CC
1, 2, 3
Switching Characteristics
Parameter
Subgroups
t
SA
7, 8, 9, 10, 11
t
HA
7, 8, 9, 10, 11
t
CO
7, 8, 9, 10, 11
SMD Cross Reference
SMD
Number
Suffix
Cypress
Number
5962-88735
033X
CY7C245A-25LMB
5962-88735
04LX
CY7C245A-25DMB
CY7C245A
Document #: 38-04007 Rev. *B
Page 8 of 11
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
CY7C245A
Document #: 38-04007 Rev. *B
Page 9 of 11
Package Diagrams
(continued)
51-85013-*A
24-Lead (300-Mil) Molded DIP P13
28-Pin Windowed Leadless Chip Carrier Q64
MILSTD1835 C4
51-80102-**
CY7C245A
Document #: 38-04007 Rev. *B
Page 10 of 11
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
(continued)
24-Lead (300-Mil) Molded SOIC S13
51-85025-*A
51-80086-**
24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
CY7C245A
Document #: 38-04007 Rev. *B
Page 11 of 11
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
113863
3/6/02
DSG
Change from Spec number: 38-00074 to 38-04007
*A
118894
10/09/02
GBI
Update ordering information
*B
122248
12/27/02
RBI
Add power up requirements to Operating Conditions information
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