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Datasheet: AT17LV512A-10JC (ATMEL Corporation)

FPGA Serial Configuration Memories

 

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ATMEL Corporation
1
Features
·
Serial EEPROM Family for Configuring Altera FLEX
®
®
®
®
10K Devices
·
Simple, Easy-to-use 4-pin Interface
·
E
2
Programmable 1M Bit Serial Memories Designed To Store Configuration Programs
For Programmable Gate Arrays
·
Cascadable To Support Additional Configurations or Future Higher-density Arrays
·
Low-power CMOS EEPROM Process
·
Programmable Reset Polarity
·
Available in the Space-efficient Surface-mount PLCC Package
·
In-System Programmable Via 2-Wire Bus
·
Emulation of 24CXX Serial EPROMs
·
Available in 3.3V
±
±
±
±
10% LV and 5V
±
±
±
±
5% C Versions
Description
The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration
EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration
memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the
"devices"). The AT17A Series is packaged in the popular 20-pin PLCC package. The
AT17A Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The AT17A Series organization supplies enough memory to configure
one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user
can select the polarity of the reset function by programming an EEPROM byte. The
AT17C/LV512/010A parts generate their own internal clock and can be used as a sys-
tem "master" for loading the FPGA devices.
The Atmel devices also supports a system friendly READY pin and a write protect
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the device memory during in-system programming.
The AT17A Series can be programmed with industry standard programmers.
FPGA Serial
Configuration
Memories
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
Rev. 0974A­04/98
Pin Configurations
20-Pin PLCC
4
5
6
7
8
18
17
16
15
14
DCLK
WP1
NC
NC
RESET/OE
SER_EN
NC
NC
READY
NC
3
2
1
20
19
9
10
11
12
13
nCS
GND
NC
nCASC
NC
NC
DATA
NC
VCC
NC
AT17C/LV/512A/010A
2
Block Diagram
Device Configuration
The control signals for configuration EEPROMs­nCS, OE,
and DCLK­interface directly with the FPGA device control
signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration
EEPROM without requiring an external intelligent control-
ler.
The configuration EEPROM device's OE and nCS pins
control the tri-state buffer on the DATA output pin and
enable the address counter and the oscillator. When OE is
driven low, the configuration EEPROM device resets the
address counter and tri-states its DATA pin. The nCS pin
controls the output of the AT17A Series. If nCS is held high
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven low, the
counter and the DATA output pin are enabled. When OE is
driven low again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of the
nCS.
When the configurator has driven out all of its data and
nCASC is driven low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up,
the address counter is automatically reset.
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series
EEPROM. The AT17A Series device stores configuration
data in its EEPROM array and clocks the data out serially
with its internal oscillator. The OE, nCS, and DCLK pins
supply the control signals for the address counter and the
output tri-state buffer. The AT17A Series device sends a
serial bitstream of configuration data to its DATA pin, which
is connected to the DATA0 input pin on the FPGA device.
When configuration data for a FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together. When multi-
ple AT17A Series devices are required, the nCASC and
nCS pins provide handshaking between the AT17A Series
devices.
The position of an AT17A Series device in a chain deter-
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS low and
is configured for FPGA devices protocol. This AT17A
Series device supplies all clock pulses to one or more
FPGA devices and to any downstream AT17A Series dur-
ing configuration. The first AT17A Series device also pro-
vides the first stream of data to the FPGA devices during
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
5
11
24/32
24/32
nCS
DCLK
OE
nCASC
DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
SER_EN
AT17C/LV/512A/010A
3
multi-device configuration. Once the first AT17A Series
device finishes sending configuration data, it drives its
nCASC pin low, which drives the nCS pin of the second
AT17A Series device low. This activates the second AT17A
Series device to send configuration data to the FPGA
device.
The first AT17A Series device clocks all subsequent AT17A
Series devices until configuration is complete. Once all
configuration data is transferred and nCS on the first
AT17A Series device is driven high by CONF_DONE on
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device. Then the
first AT17A Series device goes into zero-power (idle) state.
If nCS on the first AT17A Series device is driven high
before all configuration data is transferred­or if the nCS is
not driven high after all configuration data is transferred­
the nSTATUS is driven low, indicating a configuration error.
Figure 1. FPGA Device Configured with Two AT17A Series Devices
nCE
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
Device 1
AT17C010A
Device 1
AT17C010A
Device 2
OE
nCASC
nCS
GND
GND
VCC
VCC
VCC
1K
W
1K
W
DATA
DCLK
OE
nCS
DATA
DCLK
AT17C/LV/512A/010A
4
Pin Configurations
Pin Number
(20-Pin PLCC)
Pin Name
Pin Type
Description
2
DATA
Output
Serial data output.
4
DCLK
I/O
Clock output or clock input. Rising edges on DCLK increment the internal address
counter and present the next bit of data to the DATA pin. The counter is incremented
only if the OE input is held high, the nCS input is held low, and all configuration data
has not been transferred to the target device (otherwise, in FPGA 10K master mode,
the DCLK pin drives low).
5
WP1
Input
WRITE PROTECT (1). Used to protect portions of memory during programming. See
programming guide for details.
8
RESET/OE
Input
Output enable (active high) and reset (active low). A low logic level resets the address
counter. A high logic level enables DATA and permits the address counter to count. In
the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK
drives low.
9
nCS
Input
Chip select input (active low). A low input allows DCLK to increment the address
counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the
device initializes as the first device in a daisy-chain. If the AT17A Series is reset with
nCS high, the device initializes as the next AT17A Series device in the chain
10
GND
Ground
A 0.2
µ
F decoupling capacitor should be placed between the V
CC
and GND pins.
12
nCASC
Output
Cascade select output (active low). This output goes low when the address counter
has reached its maximum value. In a daisy-chain of AT17A Series devices, the
nCASC pin of one device is usually connected to the nCS input pin of the next device
in the chain, which permits DCLK to clock data from the next AT17A Series device in
the chain.
A2
Input
Device selection input, A2. This is used to enable (or select) the device during
programming, when SER_EN is Low (see Programming Guide for more details)
15
READY
Output
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (Recommend a 4.7K
Pull-up on this pin if used).
18
SER_EN
Input
Serial enable is normally high during FPGA loading operations. Bringing SER_EN
Low, enables the two wire serial interface mode for programming.
20
V
CC
Power
Power pin.
Absolute Maximum Ratings*
Operating Temperature .................................. -55
°
C to +125
°
C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
Storage Temperature ..................................... -65
°
C to +150
°
C
Voltage on Any Pin
with Respect to Ground .............................-0.1V to V
CC
+ 0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 s @ 1/16 in.)..................260
°
C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF) ................................ 2000V
AT17C/LV/512A/010A
5
Operating Conditions
Symbol
Description
AT17CXXXA
AT17LVXXXA
Units
Min
Max
Min
Max
V
CC
Commercial
Supply voltage relative to GND
-0
°
C to +70
°
C
4.75
5.25
3.0
3.6
V
Industrial
Supply voltage relative to GND
-40
°
C to +85
°
C
4.5
5.5
3.0
3.6
V
Military
Supply voltage relative to GND
-55
°
C to +125
°
C
4.5
5.5
3.0
3.6
V
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