EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration
memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the
"devices"). The AT17A Series is packaged in the popular 20-pin PLCC package. The
AT17A Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The AT17A Series organization supplies enough memory to configure
one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user
can select the polarity of the reset function by programming an EEPROM byte. The
AT17C/LV512/010A parts generate their own internal clock and can be used as a sys-
tem "master" for loading the FPGA devices.
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the device memory during in-system programming.
and DCLKinterface directly with the FPGA device control
signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration
EEPROM without requiring an external intelligent control-
control the tri-state buffer on the DATA output pin and
enable the address counter and the oscillator. When OE is
driven low, the configuration EEPROM device resets the
address counter and tri-states its DATA pin. The nCS pin
controls the output of the AT17A Series. If nCS is held high
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven low, the
counter and the DATA output pin are enabled. When OE is
driven low again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of the
nCASC is driven low, the device tri-states the DATA pin to
avoid contention with other configurators. Upon power-up,
the address counter is automatically reset.
EEPROM. The AT17A Series device stores configuration
data in its EEPROM array and clocks the data out serially
with its internal oscillator. The OE, nCS, and DCLK pins
supply the control signals for the address counter and the
output tri-state buffer. The AT17A Series device sends a
serial bitstream of configuration data to its DATA pin, which
is connected to the DATA0 input pin on the FPGA device.
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together. When multi-
ple AT17A Series devices are required, the nCASC and
nCS pins provide handshaking between the AT17A Series
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS low and
is configured for FPGA devices protocol. This AT17A
Series device supplies all clock pulses to one or more
FPGA devices and to any downstream AT17A Series dur-
ing configuration. The first AT17A Series device also pro-
vides the first stream of data to the FPGA devices during
device finishes sending configuration data, it drives its
nCASC pin low, which drives the nCS pin of the second
AT17A Series device low. This activates the second AT17A
Series device to send configuration data to the FPGA
Series devices until configuration is complete. Once all
configuration data is transferred and nCS on the first
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device. Then the
first AT17A Series device goes into zero-power (idle) state.
If nCS on the first AT17A Series device is driven high
before all configuration data is transferredor if the nCS is
not driven high after all configuration data is transferred
the nSTATUS is driven low, indicating a configuration error.
counter and present the next bit of data to the DATA pin. The counter is incremented
only if the OE input is held high, the nCS input is held low, and all configuration data
has not been transferred to the target device (otherwise, in FPGA 10K master mode,
the DCLK pin drives low).
programming guide for details.
counter. A high logic level enables DATA and permits the address counter to count. In
the mode, if this pin is low (reset), the internal oscillator becomes inactive and DCLK
counter and enables DATA to drive out. If the AT17A Series is reset with nCS low, the
device initializes as the first device in a daisy-chain. If the AT17A Series is reset with
nCS high, the device initializes as the next AT17A Series device in the chain
has reached its maximum value. In a daisy-chain of AT17A Series devices, the
nCASC pin of one device is usually connected to the nCS input pin of the next device
in the chain, which permits DCLK to clock data from the next AT17A Series device in
programming, when SER_EN is Low (see Programming Guide for more details)
power-up is complete. (Recommend a 4.7K
Low, enables the two wire serial interface mode for programming.
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
with Respect to Ground .............................-0.1V to V