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Datasheet: AT17LV512/010 (ATMEL Corporation)

Fpga Configuration EePROM Memory 512k and 1m

 

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ATMEL Corporation

Document Outline

1
Features
EE Programmable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
In-System Programmable via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K FPGAs, Altera FLEX
Devices, Lucent ORCA
FPGAs, Xilinx XC3000, XC4000, XC5200, SPARTAN
and Virtex
FPGAs
Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in PLCC Package (Pin-compatible Across Product Family)
Emulation of Atmel's AT24CXXX Serial EEPROMs
Available in 3.3V 10% LV and 5V 5% C Versions
System-friendly READY Pin
Low-power Standby Mode
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configu-
ration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The AT17 Series is packaged in the
popular 20-pin PLCC. The AT17 Series family uses a simple serial-access procedure
to configure one or more FPGA devices. The AT17 Series organization supplies
enough memory to configure one or multiple smaller FPGAs. The user can select the
polarity of the reset function by programming four EEPROM bytes. These devices
also support a write protection mode and a system-friendly READY pin, which signi-
fies a "good" power level to the FPGA and can be used to ensure reliable system
power-up.
The AT17 Configurator Series can be programmed with industry-standard program-
mers, or Atmel's ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
512K and 1M
AT17C512
AT17LV512
AT17C010
AT17LV010
Rev. 0944B07/99
Pin Configurations
PLCC
4
5
6
7
8
18
17
16
15
14
CLK
WP1
RESET/OE
WP2
CE
NC
SER_EN
NC
READY
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
NC
NC
NC
NC
DATA
NC
VCC
NC
AT17C/LV512/010
2
Block Diagram
FPGA Master Serial Mode Summary
The I/O and logic functions of the FPGA and their associ-
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power-up, or on command, depending on the state of the
FPGA mode pins. In Master Mode, the FPGA automatically
loads the configuration program from an external memory.
The AT17 Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
This document discusses the AT40K FPGA interface. For
more details or AT6000 FPGA applications, please refer-
ence "AT40K Series Configuration" or "AT6000 Series
Configuration" application notes.
Controlling the High-density AT17
Series Serial EEPROMs During
Configuration
Most connections between the FPGA device and the AT17
Serial Configuration EEPROM are simple and self-
explanatory:
The DATA output of the AT17 Series Configurator drives
DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of
the AT17 Series Configurator.
The CEO output of any AT17C/LV512/010 drives the CE
input of the next AT17C/LV512/010 in a cascade chain of
EEPROMs.
SER_EN must be connected to VCC, (except during
ISP).
The READY pin is available as an open-collector indicator
of the device's reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete.
There are two different ways to use the inputs CE and OE.
Condition 1
The simplest connection is to have the FPGA CON pin
drive both CE and RESET/OE
(1)
in parallel. Due to its sim-
plicity, however, this method will fail if the FPGA receives
an external reset condition during the configuration cycle. If
a system reset is applied to the FPGA, it will abort the origi-
n a l c o n f i g u r a t i o n a n d t h e n r e s e t i t s e l f f o r a n e w
configuration, as intended. Of course, the AT17 Series
Configurator does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Note:
1. For this condition, the reset polarity of the EEPROM
must be set active High.
AT17C/LV512/010
3
Figure 1. Condition 2 Connection
Notes:
1. Use of the READY pin is optional.
2. Reset polarity of EEPROM must be set active Low.
Condition 2
The FPGA CON output drives only the CE input of the
AT17 Series Configurator, while the RESET/OE input is
driven by the FPGA INIT pin (Figure 1). This connection
works under all normal circumstances, even when the user
aborts a configuration before CON has gone high. A Low
level on the RESET/OE
(1)
input during FPGA reset
clears the Configurator's internal address pointer, so that
the reconfiguration starts at the beginning.
Note:
1. For this condition the reset polarity of the EEPROM
must be set active Low.
The AT17 Series Configurator does not require an inverter
f o r e i t h e r c o n d i t i o n s i n c e t h e R E S E T p o l a r i t y i s
programmable.
Cascading Serial Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories, cas-
caded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock
signal to the Configurator asserts its CEO output Low and
disables its DATA line driver. The second Configurator rec-
ognizes the Low level on its CE input and enables its DATA
output.
After configuration is complete, the address counters of all
cascaded Configurators are reset if the RESET/OE on
each Configurator is driven to its active (default High) level.
If the address counters are not to be reset upon comple-
tion, then the RESET/OE input can be tied to its inactive
(default Low) level.
AT17 Series Reset Polarity
The AT17 Series Configurator allows the user to program
the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer
a l g o ri t h m s . Fo r m o re d e t a i l s o n p ro g r a m m i n g t h e
EEPROMs reset polarity, please reference the "Program-
ming Specification for Atmel's FPGA Configuration
EEPROMs" application note.
Programming Mode
The programming mode is entered by bringing SER_EN
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the "Programming Specification for Atmel's
FPGA Configuration EEPROMs" application note for fur-
ther information. The AT17C parts are read/write at 5V
nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV512/010 Series Configurator enters a low-
power standby mode whenever CE is asserted High. In this
mode, the Configurator consumes less than 0.5 mA of cur-
rent at 5V. The output remains in a high impedance state
regardless of the state of the OE input.
M0
INIT
M1
CON
CCLK
D<0>
RESET
RESET
AT40K
AT17C512/010
AT17LV512/010
GND
VCC
RESET/OE
READY
SER_EN
CE
CLK
DATA
M2
AT17C/LV512/010
4
Pin Configurations
20
PLCC
Pin
Name
I/O
Description
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
4
CLK
I
Clock input. Used to increment the internal address and bit counter for reading and
programming.
5
WP1
I
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the "Programming Specification" application note for more details.
6
RESET/OE
I
RESET/Output Enable input (when SER_EN is High). A Low level on both the CE and
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets both the
address and bit counters. The logic polarity of this input is programmable as either RESET/OE
or RESET/OE. This document describes the pin as RESET/OE.
7
WP2
I
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. See the "Programming Specification" application note for more details.
8
CE
I
Chip Enable input. Used for device selection. A Low level on both CE and OE enables the data
output driver. A High level on CE disables both the address and bit counters and forces the
device into a low-power standby mode. Note that this pin will not enable/disable the device in
the 2-wire Serial Programming Mode (i.e., when SER_EN is Low).
10
GND
Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended.
14
CEO
O
Chip Enable Output. This signal is asserted Low on the clock cycle following the last bit read
from the memory. It will stay Low as long as CE and OE are both Low. It will then follow CE until
OE goes High. Thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device during programming
(i.e., when SER_EN is Low; see the "Programming Specification" application note for
more details).
15
READY
O
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. (Recommend a 4.7 k
pull-up on this pin if used).
17
SER_EN
I
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low
enables the 2-wire Serial Programming Mode.
20
VCC
+3.3V/+5V power supply pin.
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Rat-
ings conditions for extended periods of time may
affect device reliability.
Storage Temperature ..................................... -65C to +150C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to V
CC
+0.5V
Supply Voltage (V
CC
) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260C
ESD (R
ZAP
= 1.5K, C
ZAP
= 100 pF) ................................ 2000V
AT17C/LV512/010
5
Operating Conditions
Symbol
Description
AT17CXXX
AT17LVXXX
Units
Min/Max
Min/Max
V
CC
Commercial
Supply voltage relative to GND
-0C to +70C
4.75/5.25
3.0/3.6
V
Industrial
Supply voltage relative to GND
-40C to +85C
4.5/5.5
3.0/3.6
V
Military
Supply voltage relative to GND
-55C to +125C
4.5/5.5
3.0/3.6
V
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