- Pin Configurations
- Block Diagram
- FPGA Master Serial Mode Summary
- Controlling the Low-density AT17 Series Serial EEPROMs During Configuration
- Cascading Serial Configuration EEPROMs (AT17C/LV128 and AT17C/LV256 only)(1)
- AT17 Series Reset Polarity
- Programming Mode
- Standby Mode
- Pin Configurations
- Absolute Maximum Ratings*
- Operating Conditions
- DC Characteristics
- DC Characteristics
- AC Characteristics
- AC Characteristics When Cascading
- AC Characteristics for AT17C65/128
- AC Characteristics for AT17C128 When Cascading
- AC Characteristics for AT17C256
- AC Characteristics for AT17C256 When Cascading
- AC Characteristics for AT17LV65/128/256
- AC Characteristics for AT17LV128/256 When Cascading
- Ordering Information - 5V Devices
- Ordering Information - 3.3V Devices
Designed to Store Configuration Programs for Field Programmable Gate
Arrays (128K and 256K only)
Pin-compatible Across Product Family
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for Field Programmable Gate Arrays. The low-density AT17 Series
is packaged in the 8-pin DIP and the popular 20-pin PLCC and SOIC. The AT17
Series family uses a simple serial-access procedure to configure one or more FPGA
devices. The AT17 Series organization supplies enough memory to configure one or
multiple smaller FPGAs. Using a feature of the AT17 Series, the user can select the
polarity of the reset function by programming a special EEPROM byte. These devices
also support a write-protection mechanism within its programming mode.
mers, or Atmel's ATDH2200E Programming Kit.
ated interconnections are established by a configuration
program. The program is loaded either automatically upon
power-up, or on command, depending on the state of the
FPGA mode pins. In Master Mode, the FPGA automatically
loads the configuration program from an external memory.
The AT17 Serial Configuration EEPROM has been
designed for compatibility with the Master Serial Mode.
more details or AT40K FPGA applications, please refer-
ence "AT6000 Series Configuration" or "AT40K Series
Configuration" application notes.
Series Serial EEPROMs During
Serial EEPROM are simple and self-explanatory.
· The DATA output of the AT17 Series Configurator drives
EEPROMs. An AT17C/LV65 can only be used at the end
of a cascade chain or as a standalone device.
drive both CE and RESET/OE
receives an external reset condition during the configura-
tion cycle. If a system reset is applied to the FPGA, it will
abort the original configuration and then reset itself for a
new configuration, as intended. Of course, the AT17 Series
Configurator does not see the external reset signal and will
not reset its internal address counters and, consequently,
will remain out of sync with the FPGA for the remainder of
the configuration cycle.
Series Configurator, while the RESET/OE input is driven by
an input to the FPGA RESET input pin. This connection
works under all normal circumstances, even when the user
aborts a configuration before CON has gone High. A Low
level on the RESET/OE
the reconfiguration starts at the beginning.
inverter for either condition since the RESET polarity is
(AT17C/LV128 and AT17C/LV256 only)
future FPGAs requiring larger configuration memories,
cascaded Configurators provide additional memory.
clock signal to the Configurator asserts its CEO output low
and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its
cascaded Configurators are reset if the RESET/OE on
each Configurator is driven to its active (default High) level.
tion, then the RESET/OE input can be tied to its inactive
(default Low) level.
the reset polarity as either RESET/OE or RESET/OE. This
feature is supported by industry-standard programmer
a l g o ri t h m s . Fo r m o re d e t a i l s o n p ro g r a m m i n g t h e
EEPROM's reset polarity, please reference the "Program-
ming Specification for Atmel's FPGA Configuration
EEPROMs" application note.
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the
chip. See the "Programming Specification for Atmel's
FPGA Configuration EEPROMs" application note for
further information. The AT17C parts are read/write at 5V
nominal. The AT17LV parts are read/write at 3.3V nominal.
mode whenever CE is asserted High. In this mode, the
Configurator consumes less than 75 µA of current at 5.0V.
The output remains in a high impedance state regardless of
the state of the OE input.
RESET/OE inputs enables the data output driver. A High level on RESET/OE resets
both the address and bit counters. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. This document describes the pin as RESET/OE.
be written. When WP is enabled (High), the lowest block of the memory cannot be
written. This feature is only active in the 2-wire serial Programming Mode (i.e., when
SER_EN is Low; see "Programming Specification" application note for more details).
the data output driver. A High level on CE disables both the address and bit counters
and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming Mode (i.e., when SER_EN
read from the memory. It will stay Low as long as CE and OE are both Low. It will then
follow CE until OE goes High. Thereafter, CEO will stay High until the entire EEPROM
is read again.
programming (i.e. when SER_EN is Low; see the "Programming Specification"
application note for more details.
Low enables the 2-wire Serial Programming Mode.
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
with Respect to Ground ..............................-0.1V to V