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Datasheet: AT17LV010-10DP-MQ (ATMEL Corporation)

Space FPGA Configuration EEPROM

 

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ATMEL Corporation

Document Outline

Rev. 4265B­AERO­06/04
1
Features
·
EE Programmable 1,048,576 x 1-bit Serial Memory Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
·
Very Low-power CMOS EEPROM Process
·
In-System Programmable (ISP) via Two-Wire Bus
·
Simple Interface to SRAM FPGAs
·
Compatible with AT40K Devices
·
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
·
Programmable Reset Polarity
·
Low-power Standby Mode
·
High-reliability
­ Endurance: 5,10
(4)
Read Cycles
·
Data Retention: 10 Years
·
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm
2
·
Tested up to a Total Dose of 20 krads (Si) according to MIL STD 883 Method 1019
·
Operating Range: 3.0V to 3.6V, -55°C to +125°C
·
Available in 400 mils Wide 28 Pins DIL Flat Pack
Description
The AT17LV010-10DP is a FPGA Configuration EEPROM provides an easy-to-use,
cost-effective configuration memory for Field Programmable Gate Arrays. It is pack-
aged in the 28-pin 400 mils wide FP package. Configurator uses a simple serial-
access procedure to configure one or more FPGA devices. The user can select the
polarity of the reset function by programming four EEPROM bytes. The device also
supports a write-protection mechanism within its programming mode.
Space FPGA
Configuration
EEPROM
AT17LV010-
10DP
Advance
Information
Rev. 4265B­AERO­06/04
2
A717LV010-10DP
4265B­AERO­06/04
Pin Configuration
Figure 1. 28-pin Flat Pack
1
2
3
4
5
6
7
8
9
10
RESET/OE
NC
WP2
CE
GND
NC
NC
NC
NC
NC
NC
WP1
CLK
DATA
NC
NC
NC
NC
VCC
28
27
26
23
22
21
20
19
18
17
16
NC
CE0
NC
NC
READY
15
24
25
NC
NC
SER_EN
NC
3
A717LV010-10DP
4265B­AERO­06/04
Block Diagram
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV010-10DP configurator. If CE is held High
after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
POWER ON
RESET
SER_EN
WP1
WP2
READY
4
A717LV010-10DP
4265B­AERO­06/04
Pin Description
DATA
T ri -state DATA output for confi guration. Open-collector bi-directional pin for
programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WP1
WRITE PROTECT (1). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations.
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
Ground pin. A 0.2 µF decoupling capacitor between V
CC
and GND is recommended.
CEO
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV010-10DP devices, the CEO pin
of one device must be connected to the CE input of the next device in the chain. It will
stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 k
pull-up resistor when this pin
is used.
SER_EN
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to V
CC
.
V
CC
3.3V (±0.3V).
5
A717LV010-10DP
4265B­AERO­06/04
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40KEL applications.
Control of
Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are sim-
ple and self-explanatory.
·
The DATA output of the AT17LV010-10DP configurator drives DIN of the FPGA
devices.
·
The master FPGA CCLK output drives the CLK input of the AT17LV010-10DP
configurator.
·
The CEO output of any AT17LV010-10DP configurator drives the CE input of the
next configurator in a cascaded chain of EEPROMs.
·
SER_EN must be connected to V
CC
(except during ISP).
·
The READY pin is available as an open-collector indicator of the device's reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
Reset PAT17LV010-
10DPolarity
The AT17LV010-10DP configurator allows the user to program the reset polarity as
either RESET/OE or RESET/OE. This feature is supported by industry-standard pro-
grammer algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at V
CC
supply
only. Programming super voltages are generated inside the chip.
Standby Mode
The AT17LV010-10DP configurator enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17LV010-10DP configurator consumes less than
100 µA of current at 3.3V. The output remains in a high-impedance state regardless of
the state of the OE input.
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