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Datasheet: AT17LV002A (ATMEL Corporation)

FPGA Configuration EEPROM Memory

 

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ATMEL Corporation

Document Outline

1
Features
Serial EEPROM Family for Configuring FLEX
Devices
Simple Interface to SRAM FPGAs
EE Programmable 2-Mbit Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future Higher-density
Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable via 2-wire Bus
Emulation of Atmel's AT24CXXX Serial EEPROMs
Available in 3.3V 5% LV and 5V 5% C Versions
System-friendly READY Pin
Replacement for AT17C/LV002A
Description
The AT17C002A and AT17LV002A (high-density AT17A Series) FPGA Configuration
EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Altera FLEX devices. The AT17A Series is packaged in the
popular 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple
serial-access procedure to configure one or more FPGA devices. The AT17A Series
organization supplies enough memory to configure one or multiple smaller FPGAs.
Using a feature of the AT17A Series, the user can select the polarity of the reset func-
tion by programming internal EEPROM bytes. The AT17A parts generate their own
internal clock and can be used as a system "master" for loading the FPGA devices.
The Atmel devices also support a system-friendly READY pin. The READY pin is used
to simplify system power-up considerations.
The AT17A Series Configurators can be programmed with industry-standard program-
mers or Atmel's ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
2-megabit
Altera Pinout
AT17C002A
AT17LV002A
Rev. 2280B08/01
2
AT17C/LV002A
2280B08/01
Block Diagram
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
nCS
DCLK READY
OE
nCASC (A2)
DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER-ON
RESET
SER_EN
WP1
32-lead TQFP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
DCLK
NC
WP1
NC
NC
OE
NC
NC
SER_EN
NC
NC
READY
NC
NC
NC
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
NC
nCS
NC
GND
NC
NC
(A2) nCASC
NC
NC
DATA
NC
NC
NC
VCC
NC
NC
Pin Configuration
20-lead PLCC
4
5
6
7
8
18
17
16
15
14
DCLK
WP1
NC
NC
OE
SER_EN
NC
NC
READY
NC
3
2
1
20
19
9
10
11
12
13
nCS
GND
NC
(A2) nCASC
NC
NC
DATA
NC
VCC
NC
3
AT17C/LV002A
2280B08/01
Device
Configuration
The control signals for the configuration EEPROM (nCS, OE and DCLK) interface directly with
the FPGA device control signals. All FPGA devices can control the entire configuration pro-
cess and retrieve data from the configuration EEPROM without requiring an external intelligent
controller.
The configuration EEPROM's OE and nCS pins control the tri-state buffer on the DATA output
pin and enable the address counter and the oscillator. When OE is driven Low, the configura-
tion EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also
controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset
pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low,
the counter and the DATA output pin are enabled. When OE is driven Low again, the address
counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.
When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other Configurators. Upon power-up, the address
counter is automatically reset.
The READY pin is available as an open-collector indicator of the device's reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete.
This document discusses the EPF10K device interface. For more details or information on
other Altera applications, please reference the "AT17A Series Conversions from Altera FPGA
Serial Configuration Memories" application note.
FPGA Device
Configuration
FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The AT17A
Series device stores configuration data in its EEPROM array and clocks the data out serially
with its internal oscillator. The OE, nCS and DCLK pins supply the control signals for the
address counter and the output tri-state buffer. The AT17A Series device sends a serial bit-
stream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the
FPGA device.
When the configuration data for an FPGA device exceeds the capacity of a single AT17A
Series device, multiple AT17A Series devices can be serially linked together (see Figure 2).
When multiple AT17A Series devices are required, the nCASC and nCS pins provide hand-
shaking between the cascaded EEPROMs.
The position of an AT17A Series device in a chain determines its operation. The first AT17A
Series device in a configurator chain is powered up or reset with nCS Low and is configured
for the FPGA device's protocol. This AT17A Series device supplies all clock pulses to one or
more FPGA devices and to any downstream AT17A Series Configurator during configuration.
The first AT17A Series Configurator also provides the first stream of data to the FPGA devices
during multi-device configuration. Once the first AT17A Series device finishes sending config-
uration data, it drives its nCASC pin Low, which drives the nCS pin of the second AT17A
Series device Low. This activates the second AT17A Series device to send configuration data
to the FPGA device.
4
AT17C/LV002A
2280B08/01
Figure 1. Configuration with a Single AT17A Series Configurator
(1)(2)(3)
Notes:
1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that V
CC
(5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High).
Figure 2. Configuration with Multiple AT17A Series Configurators
(1)(2)(3)
Notes:
1. Use of the READY pin is optional.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that V
CC
(5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High).
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF6K/EPF10K
AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A
GND
OE
nCS
DATA
DCLK
nCE
READY
V
CC
SER_EN
V
CC
V
CC
V
CC
0.1
mF
1 k
W
1 k
W
1 k
W
MSEL1
nSTATUS
MSEL0
CONF_DONE
DATA0
DCLK
nCONFIG
EPF10K
AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A
DEVICE 1
GND
OE
nCS
nCASC
DATA
DCLK
AT17C512A/010A/020A/002A
AT17LV512A/010A/020A/002A
DEVICE 2
OE
nCS
DATA
DCLK
READY
V
CC
V
CC
V
CC
1 k
W
1 k
W
1 k
W
nCE
SER_EN
V
CC
0.1
mF
5
AT17C/LV002A
2280B08/01
The READY pin is available as an open-collector indicator of the device's reset status; it is
driven Low while the device is in its power-on reset cycle and released (tri-stated) when the
cycle is complete. It can be used to hold the FPGA device in reset while it is completing its
power-on reset but it cannot be used to effectively delay configuration (i.e., the output is
released well before the system V
CC
has stabilized).
The first AT17A Series device clocks all subsequent AT17A Series devices until configuration
is complete. Once all configuration data is transferred and nCS on the first AT17A Series
device is driven High by CONF_DONE on the FPGA devices, the first AT17A Series device
clocks 16 additional cycles to initialize the FPGA device before going into zero-power (idle)
state. If nCS on the first AT17A Series device is driven High before all configuration data is
transferred or if the nCS is not driven High after all configuration data is transferred nSTA-
TUS is driven Low, indicating a configuration error.
AT17A Series
Reset Polarity
The AT17A Series Configurator allows the user to program the polarity of the OE pin as either
RESET/OE or RESET/OE. For more details, please reference the "Programming Specification
for Atmel's FPGA Configuration EEPROMs" application note.
Programming
Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be
programmed by the 2-wire serial interface. The programming is done at V
CC
supply only. Pro-
gramming supervoltages are generated inside the chip. See the "Programming Specification
for Atmel's Configuration EEPROMs" application note for further information. The AT17 A-
series parts are read/write at 5V nominal. The AT17LV A-series parts are read/write at 3.3V
nominal.
Standby Mode
The AT17A Series Configurator enters a low-power standby mode whenever nCS is asserted
High. In this mode, the configuration consumes less than 0.5 mA of current at 5V. The output
remains in a high-impedance state regardless of the state of the OE input.
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