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Datasheet: AT17F040-30BJI (ATMEL Corporation)

4 Mbit In-system Programable Prom (3.3V)

 

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ATMEL Corporation
1
Features
·
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
·
3.3V Output Capability
·
5V Tolerant I/O Pins
·
In-System Programmable (ISP) via 2-wire Bus
·
Simple Interface to SRAM FPGAs
·
Compatible with Atmel AT40K and AT94K Devices, Altera FLEX
®
, APEX
TM
Devices,
Lucent ORCA
®
FPGAs, Xilinx XC3000
TM
, XC4000
TM
, XC5200
TM
, Spartan
®
, Virtex
®
FPGAs,
Motorola MPA1000 FPGAs
·
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
·
Low-power CMOS FLASH Process
·
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages
·
Emulation of Atmel's AT24CXXX Serial EEPROMs
·
Low-power Standby Mode
·
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
·
Fast Serial Download Speeds up to 33 MHz
Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC,
44-lead PLCC and 44-lead TQFP, see Table 1. The AT17F Series Configurator uses a
simple serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.
Table 1. AT17F Series Packages
Package
AT17F040
AT17F080
8-lead LAP
Yes
Yes
20-lead PLCC
Yes
Yes
44-lead PLCC
­
Yes
44-lead TQFP
­
Yes
In-System
Programmable
Configuration
PROM
AT17F040
AT17F080
Advance
Information
Rev. 3039D­CNFG­4/03
2
AT17F040/080
3039D­CNFG­4/03
Pin Configuration
8-lead LAP
20-lead PLCC
8
7
6
5
1
2
3
4
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
4
5
6
7
8
18
17
16
15
14
CLK
NC
RESET/OE
PAGESEL1
CE
NC
SER_EN
PAGE_EN
READY
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
PAGESEL0
NC
NC
NC
DATA
NC
VCC
NC
3
AT17F040/080
3039D­CNFG­4/03
44 PLCC
44 TQFP
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO/A2
NC
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
4
AT17F040/080
3039D­CNFG­4/03
Block Diagram
Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK)
interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration device without
requiring an external intelligent controller.
The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and
enable the address counter. When RESET/OE is driven Low, the configuration device
resets its address counter and tri-states its DATA pin. The CE pin also controls the out-
put of the AT17F Series Configurator. If CE is held High after the RESET/OE reset
pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subse-
quently driven High, the counter and the DATA output pin are enabled. When
RESET/OE is driven Low again, the address counter is reset and the DATA output pin is
tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset
5
AT17F040/080
3039D­CNFG­4/03
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK
Clock input. Used to increment the internal address and bit counter for reading and
programming.
PAGE_EN
Input used to enable page download mode. When PAGE_EN is high the configuration
download address space is partitioned into 4 equal pages. This gives users the ability to
easily store and retrieve multiple configuration bitstreams from a single configuration
device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be
held low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no
effect.
PAGESEL[1:0]
Page select inputs. Used to determine which of the 4 memory pages are targeted during
a serial configuration download. The address space for each of the pages is shown in
Table 2. When SER_EN is Low (ISP mode) these pins have no effect.
Pin Description
Name
I/O
AT17F040
AT17F080
8
LAP
20
PLCC
8
LAP
20
PLCC
44
PLCC
44
TQFP
DATA
I/O
1
2
1
2
2
40
CLK
I
2
4
2
4
5
43
PAGE_EN
I
­
16
­
16
1
39
PAGESEL0
I
­
11
­
11
20
14
PAGESEL1
I
­
7
­
7
25
19
RESET/OE
I
3
6
3
6
19
13
CE
I
4
8
4
8
21
15
GND
­
5
10
5
10
24
18
CEO
O
6
14
6
14
27
21
A2
I
READY
O
­
15
­
15
29
23
SER_EN
I
7
17
7
17
41
35
V
CC
­
8
20
8
20
44
38
Table 2. Address Space
Paging Decodes
AT17F040 (4 Mbits)
AT17F080 (8 Mbits)
PAGESEL = 00, PAGE_EN = 1
00000 ­ 0FFFFh
00000 ­ 1FFFFh
PAGESEL = 01, PAGE_EN = 1
10000 ­ 1FFFFh
20000 ­ 3FFFFh
PAGESEL = 10, PAGE_EN = 1
20000 ­ 2FFFFh
40000 ­ 5FFFFh
PAGESEL = 11, PAGE_EN = 1
30000 ­ 3FFFFh
60000 ­ 7FFFFh
PAGESEL = XX, PAGE_EN = 0
00000 ­ 3FFFFh
00000 ­ 7FFFFh
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