- Pin Configurations
- Block Diagram
- Device Configuration
- AT17A Series Reset Polarity
- Programming Mode
- Standby Mode
- Pin Configurations
- Absolute Maximum Ratings*
- Operating Conditions
- DC Characteristics
- DC Characteristics
- AC Characteristics
- AC Characteristics When Cascading
- AC Characteristics for AT17C65A/128A
- AC Characteristics for AT17C128A When Cascading
- AC Characteristics for AT17C256A
- AC Characteristics for AT17C256A When Cascading
- AC Characteristics for AT17LV65A/128A/256A
- AC Characteristics for AT17LV128A/256A When Cascading
- Ordering Information - 5V Devices
- Ordering Information - 3.3V Devices
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
Arrays (128K and 256K only)
FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective
configuration memory for programming Altera FLEX
access procedure to configure one or more FPGA devices. The AT17A series organi-
zation supplies enough memory to configure one or multiple smaller FPGAs. Using a
feature of the AT17A series, the user can select the polarity of the reset function by
programming a special EEPROM byte. These devices also support a write protection
mechanism within its programming mode.
mers, or Atmel's ATDH2200E Programming Kit.
OE, and DCLK--interface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
together control the tri-state buffer on the DATA output pin
and enable the address counter. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is subsequently
driven Low, the counter and the DATA output pin are
enabled. When OE is driven Low again, the address
counter is reset and the DATA output pin is tri-stated,
regardless of the state of nCS.
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
interfaces. For more details or information on other Altera
sions from Altera FPGA Serial Configuration Memories"
Series EEPROM (Figure 1). The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially according to an external clock source.
The OE, nCS, and DCLK pins supply the control signals for
the address counter and the output tri-state buffer. The
AT17A Series device sends a serial bitstream of configura-
tion data to its DATA pin, which is connected to the DATA0
input pin on the FPGA device.
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascade chain or as a standalone device.
directly driven by the FPGA) provides the first stream of
data to the FPGA device during multi-device configuration.
Once the first AT17A Series device finishes sending config-
uration data, it drives its nCASC pin Low, which drives the
nCS pin of the second AT17A Series device Low. This
allows the second AT17A Series device to send configura-
tion data to the FPGA.
High before all configuration data is transferred--or if nCS
ferred--nSTATUS is driven Low, indicating a configuration
are not designed to act as system masters (i.e. provide
clock pulses on the serial bus to other devices). Clocking
must be supplied by an FPGA device, a high-density
AT17A Series device (Figure 2), or an external oscillator.
t he p o l a r i t y o f t h e O E p i n as eit h e r R E S E T / O E o r
RESET/OE. This feature is supported by industry standard
programmer algorithms. For more details on programming
the EEPROMs reset polarity, please reference the "Pro-
gramming Specification for Atmel's FPGA Configuration
EEPROMs" application note.
Low. In this mode the chip can be programmed by the
2-wire serial bus. The programming is done at VCC supply
chip. See the "Programming Specification for Atmel's Con-
f i g u r a t i o n E E P R O M " a p p l i c a t i o n n o t e f o r f u r t h e r
information. The AT17CxxxA parts are read/write at 5V
nominal. The AT17LVxxxA parts are read/write at 3.3V
mode whenever nCS is asserted High. In this mode,
the configurator consumes less than 75 µA of current
at 5.0V. The output remains in a high-impedance state
regardless of the state of the OE input.
level resets the address counter. A High logic level (with nCS Low) enables DATA and
permits the address counter to count. The logic polarity of OE is programmable and must
be set active High (RESET active Low) by the user during programming for Altera
SER_EN is Low). When WP is Low, the entire memory can be written. When WP is
enabled (High), the lowest block of the memory cannot be written. This function is not
available during FPGA loading operations. Please refer to the "Programming
Specification" application note for more details.
the address counter and enables DATA to drive out. A High level on nCS disables both
the address and bit counters and forces the device into a low-power standby mode. Note
that this pin will not enable/disable the device in the 2-wire Serial Programming Mode
(i.e., when SER_EN is Low).
reached its maximum value. In a daisy-chain of AT17A series devices, the nCASC pin of
one device must be connected to the nCS input pin of the next device in the chain. It will
stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE goes
Low, thereafter, nCASC will stay High until the entire EEPROM is read again.
programming (i.e., when SER_EN is Low; please refer to the "Programming
Specification" application note for more details).
enables the 2-wire Serial Programming Mode.
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
with Respect to Ground .............................. -0.1V to V