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Datasheet: AIC (ATMEL Corporation)

Advanced Interrupt Controller 32-bit Embedded Core Peripheral

 

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ATMEL Corporation

Document Outline

1
Features
·
Compatible with an Embedded ARM7TDMI
TM
Processor
·
8-level Priority
·
From 2 to 32 Interrupt Sources
·
Individually Maskable and Vectored
·
Substantially Reduces the Software and Real-time Overhead in Handling Internal and
External Interrupts
·
Includes Protect Mode Feature Via Two Primary Inputs or Via a Configuration Register
·
Can be Directly Connected to the Atmel Implementation of the AMBA
TM
Peripheral Bus
(APB)
·
Full Scan Testable (up to 99%)
Description
The advanced interrupt controller (AIC) is an 8-level priority, individually maskable,
vectored interrupt controller. It can substantially reduce the software and real-time
overhead in handling internal and external interrupts.
This peripheral can be used with any 32-bit microcontroller core if the timing diagram
shown on page 8 is respected. The interrupt handling must be performed as
described on page 6, using the corresponding assembler instructions for the 32-bit
core used.
When using an ARM7TDMI
®
as the core, the Atmel bridge must be used to provide
the correct bus interface to the AIC.
The interrupt controller can be directly connected to the nFIQ (fast interrupt request)
and the nIRQ (standard interrupt request) inputs of an ARM7TDMI processor, or the
equivalent inputs of another 32-bit microcontroller core. The processor's nFIQ line can
only be asserted by the external fast interrupt request input: FIQ. The nIRQ line can
be asserted by all the other interrupt sources.
An 8-level priority encoder allows the customer to define the priority between the dif-
ferent nIRQ interrupt sources. Internal interrupt sources are programmed to be level
sensitive or edge triggered. External interrupt sources can be programmed to be posi-
tive or negative edge triggered or high or low level sensitive.
This document describes the AIC in a specific configuration as specified below:
·
One FIQ is connected on the interrupt line[0].
·
Eight internal interrupt sources are connected on interrupt lines[8:1].
·
Three external interrupt sources are connected on interrupt lines[11:9] but are
mapped on interrupts[18:16].
The interrupt sources are listed in Table 2 and the AIC programmable registers in
Table 3. The register interaction is shown in Figure 4.
32-bit
Embedded Core
Peripheral
Advanced
Interrupt
Controller (AIC)
Rev. 1246F­CASIC­03/02
2
Advanced Interrupt Controller (AIC)
1246F­CASIC­03/02
Figure 1. AIC Pin Configuration
Notes:
1. N = Number of interrupt sources
2. N
chain
= Number of scan chains
3. These primary inputs can be replaced by a configuration register (see Table 3 on page 9 and "AIC Debug Control Register
(Protect Control Register)" on page 18.
periph_data_in[31:0]
nreset_r
periph_address[13:0]
periph_write
periph_strobe
clock
periph_select
interrupt_lines[(N-1):0]
(1)
debug_mode
(3)
scan_test_mode
debug_int_mask
(3)
nfiq
nirq
nint
test_so[N
chain
:1]
(2)
periph_data_out[31:0]
AIC
Functional
Functional
Debug
(3)
test_se
test_si[N
chain
:1]
(2)
Test Scan
Test Scan
pstb_rising
nreset_f
Table 1. Pin Description List
Name
Definition
Type
Active
Level
Comments
Functional
nreset_r
System Reset
Input
Low
Resets all counters and signals clocked on rising edge of
clock
nreset_f
System Reset
Input
Low
Resets all counters and signals clocked on falling edge of
clock
clock
System Clock
Input
­
­
periph_address[13:0]
Peripheral
Address Bus
Input
­
From host (bridge). Software user interface address bus
periph_data_in[31:0]
Peripheral
Data Bus Input
Input
­
From host (bridge). Software user interface data bus
periph_data_out[31:0]
Peripheral
Data Bus Input
Output
­
To host (bridge). Software user interface data bus
periph_write
Peripheral Write
Enable
Input
­
From host (bridge). Transfer enable. When high, indicates
that the host processor is writing to a register or executing
a command.
pstb_rising
­
Input
­
From host (bridge). Clock for all DFFs controlling
configuration registers
periph_strobe
Peripheral Strobe
Input
High
When high indicates that data and address buses are
stable
3
Advanced Interrupt Controller (AIC)
1246F­CASIC­03/02
Notes:
1. N = Number of interrupt sources
2. N
int
= Number of internal interrupt sources
3. N
ext
= Number of external interrupt sources
4. N
chain
= Number of scan chains
5. These primary inputs do not exist when the configuration register is used for the Protect Mode feature.
Scan Test Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order
to achieve this, the ATPG vectors must be generated on the entire circuit (top-level) which includes the AIC or all AIC I/Os
must have a top level access and ATPG vectors must be applied to these pins.
periph_select
Peripheral Selection
Input
High
When high, indicates that the host is accessing the AIC
interrupt_lines[(N-1):0]
(1)
Interrupt Input Lines
(Sources)
Input
­
Polarities can be defined in the configuration registers for
inputs corresponding to external interrupt sources.
Generally, they are connected as follows:
- FIQ source on interrupt_lines[0]
- N
int
internal sources on interrupt_lines[N
int
:1]
(2)
- N
ext
external sources on interrupt_lines[(N-1):(N-N
ext
)]
(1, 3)
Note: N = N
ext
+ N
int
+ 1(FIQ)
nfiq
Fast Interrupt Request
Output
Low
Destination: Input nFIQ of ARM core
Source: Fast Interrupt Request; usually connected to
interrupt_iines[0]
nirq
Interrupt Request
Output
Low
Destination: Input nIRQ of ARM core
Source: All interrupt requests (except Fast Interrupt
Request) usually connected to interrupt_lines[(N-1):1]
(1)
nint
­
Output
Low
Low if either nfiq or nirq is active. If nfiq and nirq are
disabled by debug_int_mask, nint generates an interrupt
depending on the interrupt sources
Debug (for use with AT91 Development Tools)
debug_mode
(5)
­
Input
­
Reserved. Must be set to 0 in functional mode.
debug_int_mask
(5)
­
Input
­
Reserved. Must be set to 0 in functional mode.
Test Scan
scan_test_mode
Scan Test Mode
Input
­
Must be tied to 1 during scan test. Must be tied to 0 in
functional mode.
test_se
Test Scan Shift Enable
Input
­
Scan shift enabled when tied to 1
test_si[N
chain
:1]
(4)
Test Scan Input
Input
­
Input to scan chains
test_so[N
chain
:1]
(4)
Test Scan Output
Output
­
Output from scan chains
Table 1. Pin Description List (Continued)
Name
Definition
Type
Active
Level
Comments
4
Advanced Interrupt Controller (AIC)
1246F­CASIC­03/02
Functional Description
Figure 2. Interrupt Controller Block Diagram
Figure 3. Connecting the AIC to an ARM
®
-based Microcontroller
Notes:
1. data_to_periph = signal name from Atmel Bridge, periph_data_in[31:0] = signal name from AIC peripheral,
PWDATA[31:0] = signal name from Atmel AMBA System Architecture specification.
2. data_from_periph = signal name from Atmel Bridge, periph_data_out[31:0] = signal name from AIC peripheral,
PRDATA[31:0] = signal name from Atmel AMBA System Architecture specification.
Control
Logic
Memorization
Memorization
Prioritization
Controller
nIRQ
Manager
nFIQ
Manager
FIQ(IRQ0) Source
Bus Interface
Internal Interrupt Sources
(IRQ1 - IRQ8)
External Interrupt Sources
(IRQ9 - IRQ11)
32-bit
Core
nFIQ
nIRQ
FIQ Source
Internal Interrupt Sources
(from peripheral interrupt outputs)
External Interrupt Sources IRQ0 to IRQ2
(from ASIC pads, PIO peripherals, ...)
32-bit
Core
(ARM)
nFIQ
nIRQ
interrupt_lines[0]
interrupt_lines[8:1]
interrupt_lines[11:9]
debug_int_mask
debug_mode
Atmel Bridge
PWRITE
PWDATA[31:0
](1)
PRDATA[31:0]
(2)
PSTB
PA[13:0]
PSELAIC
Atmel Bus Interface
ASB
AIC
PSTB_RISING
CLOCK
NRESET
nint
3
8
5
Advanced Interrupt Controller (AIC)
1246F­CASIC­03/02
Note:
Reserved interrupt sources are not available. Corresponding registers must not be used and read 0.
Table 2. AIC Interrupt Sources
Interrupt
Source
Interrupt Name
Interrupt
Description
(1)
Comment
AT91M40400 Interrupt Assignment
(1)
0
FIQ
Fast Interrupt
Edge/Level
Negative/Positive
Fast Interurpt
1
IRQ1
Interrupt 1
Edge/Level
Positive only
Software Interrupt
2
IRQ2
Interrupt 2
USART Channel 0 Interrupt
3
IRQ3
Interrupt 3
USART Channel 1 Interrupt
4
IRQ4
Interrupt 4
Timer Channel 0 Interrupt
5
IRQ5
Interrupt 5
Timer Channel 1 Interrupt
6
IRQ6
Interrupt 6
Timer Channel 2 Interrupt
7
IRQ7
Interrupt 7
Watchdog Interrupt
8
IRQ8
Interrupt 8
Parallel I/O interrupt
9
­
Reserved
­
Reserved
10
­
Reserved
­
Reserved
11
­
Reserved
­
Reserved
12
­
Reserved
­
Reserved
13
­
Reserved
­
Reserved
14
­
Reserved
­
Reserved
15
­
Reserved
­
Reserved
16
IRQ9
Interrupt 9
Edge/Level
Negative/Positive
External Interrupt 0
17
IRQ10
Interrupt 10
External Interrupt 1
18
IRQ11
Interrupt 11
External Interrupt 2
19
­
Reserved
­
Reserved
20
­
Reserved
­
Reserved
21
­
Reserved
­
Reserved
22
­
Reserved
­
Reserved
23
­
Reserved
­
Reserved
24
­
Reserved
­
Reserved
25
­
Reserved
­
Reserved
26
­
Reserved
­
Reserved
27
­
Reserved
­
Reserved
28
­
Reserved
­
Reserved
29
­
Reserved
­
Reserved
30
­
Reserved
­
Reserved
31
­
Reserved
­
Reserved
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