- Programming Setup
- Power Configuration
- Program/Boot Settings
- Programming the AT40K FPGA Device
- Programming the AT17 Configuration Memory Device
- Programming the PSLI Device Using the AT17 Configuration Memory
- Technical Support
- ATDH40M Functional Schematics
- ATDH40M Layout Schematics
Supports Modular Docking Platform for the ATDH40D FPGA Daughter Boards
Runs Off Portable 9V DC Power Supply or External Power
Supports 5.0V or 3.3V Supply
Designed to Work with Atmel IDS 5.0 or Above
Downloading for AT40K/AT17 Devices Direct from PC Parallel Port
Can be Used to Support FPSLIC
cally evaluate Atmel's fam ily of AT40K/AT40KAL FPGA and AT94K Field
Programmable System Level Integrated Circuit (FPSLIC
via parallel port through a 10-pin header cable to program the AT40K/AT40KAL
FPGA/AT94K FPSLIC, or through a parallel port cable to program the AT17 FPGA
Configuration EEPROMs. The motherboard interfaces with various daughter boards
in order to program different package footprints (see Table 1).
a given package footprint across the family. See Table 2 for
compatibility listings. The 208PQFP, for example, will sup-
port all AT40K family members.
families and is supported by the ATDH40M Prototyping
nect the two boards together, the daughter board fits on top of the motherboard by aligning the two arrows together. The
two boards will only fit one way.
can be supplied by either the jack inputs J1 and J2, or by a
9V power input P1. The source that will drive the mother-
board is determined by switch SW3. Power supplied by the
jacks uses the external setting. Power supplied by the
9V source uses the internal setting. Voltage on the
motherboard for the latter setting is regulated by switch
SW2. LV parts use the 3.3V setting while the rest use the
5.0V setting. The LED L1 will light up only when power is
correctly supplied to VCC. Table 3 lists the possible
configurations. AT40KAL and AT94KAL devices must use
3.5V power setting.
settings for the ATDH40M. They are located on the bottom
left corner. Table 4 lists the switch combinations and their
effects. SW4 controls the SEREN signal line of the mother-
board to the 2:1 multiplexer (device U3) and the AT17
(device U1). SW% connects signal D0 from the PSLI
device to either the AT17 configuration memory device only
(down) or to the PC interface (up).
programmed by the PC parallel interface. The ATDH40M
interfaces with the PC through the 10-pin header socket H1
located on the bottom right corner. Programming the FPGA
is not possible by using the parallel port interface on the
motherboard. Located below the header H1 are the mode-
select dip-switches DIP-SW1. These control the mode set-
tings for the PSLI device (switches M0, (M1), M2). The
modes directly supported by the motherboard are only
Slave Serial and Master Serial. Programming the AT40K
FPGA from the PC can be achieved from the IDS desktop
or by using the software downld40.exe. Both tools accept
ASCII bitstream files generated by the IDS software (.BST).
FPGA configuration memory can be programmed by the
parallel port interface located on the top left corner.
Programming the AT17 FPGA Configuration EEPROM is
not possible by using the 10-pin header H1. Programming
the AT17 FPGA Configuration EEPROM from the PC can
be achieved from the IDS desktop or by using the Configu-
rator Programming System (CPS) software supplied by the
IDS software.This software accepts the ASCII bitstream
files (.BST) generated by IDS.
the AT17 Configuration Memory
Configurator can program the FPGA in Master Serial. To
ensure reliable system power-up, set jumper JMP1
(located below the Configurator socket). The Configurator
must be programmed prior to this setup.
either through the parallel port or through the 10-pin
the power configuration switches SW2 and SW3
SW4 and SW5 are correct.
and that it receives power.
Configurator are placed in their sockets correctly.
the PSLI Device.