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Datasheet: 90S4414 (ATMEL Corporation)

8-bit Microcontroller With 4k Bytes In-system Programmable Flash


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ATMEL Corporation
- High Performance and Low Power RISC Architecture
118 Powerful Instructions - Most Single Clock Cycle Execution
4K bytes of In-System Reprogrammable Flash
­ SPI Serial Interface for Program Downloading
­ Endurance: 1,000 Write/Erase Cycles
256 bytes EEPROM
­ Endurance: 100,000 Write/Erase Cycles
256 bytes Internal SRAM
32 x 8 General Purpose Working Registers
32 Programmable I/O Lines
Programmable Serial UART
SPI Serial Interface
: 2.7 - 6.0V
Fully Static Operation
­ 0 - 8 MHz, 4.0 - 6.0V
­ 0 - 4 MHz, 2.7 - 4.0V
Up to 8 MIPS Throughput at 8 MHz
One 8-Bit Timer/Counter with Separate Prescaler
One 16-Bit Timer/Counter with Separate Prescaler
and Compare and Capture Modes
Dual PWM
External and Internal Interrupt Sources
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
Low Power Idle and Power Down Modes
Programming Lock for Software Security
The AT90S4414 is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S4414 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture that combines a rich
instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent regis-
ters to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
Rev. 0840DS­07/98
with 4K bytes
Pin Configurations
Note: This is a summary document. For the complete 76 page
datasheet, please visit our web site at
or e-
mail at
and request literature #0840D.
Block Diagram
Figure 1. The AT90S4414 Block Diagram
The AT90S4414 provides the following features: 4K bytes
of In-System Programmable Flash, 256 bytes EEPROM,
256 bytes SRAM, 32 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a pro-
grammable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
The device is manufactured using Atmel's high density
non-volatile memory technology. The on-chip In-System
Programmable Flash allows the program memory to be
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S4414 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embed-
ded control applications.
The AT90S4414
is supported with a full suite of pro-
gram and system development tools including: C compil-
ers, macro assemblers, program debugger/simulators, in-
circuit emulators, and evaluation kits.
Pin Descriptions
Supply voltage
Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port. Port pins can pro-
vide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20mA and can drive LED dis-
plays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data input/output
when using external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features
of the AT90S4414 as listed on page 45.
Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port C output buffers can sink 20 mA. As
inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port C also serves as Address output when using external
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features
of the AT90S4414 as listed on page 51.
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
Output from the inverting oscillator amplifier
ICP is the input pin for the Timer/Counter1 Input Capture
OC1B is the output pin for the Timer/Counter1 Output
CompareB function
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
Figure 2. Oscillator Connections
Figure 3. External Clock Drive Configuration
AT90S4414 Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle. Six of the 32 registers can be used as
three 16-bits indirect address register pointers for Data
Space addressing - enabling efficient address calculations.
One of the three address pointers is also used as the
address pointer for the constant table look up function.
These added function registers are the 16-bits X-register,
Y-register and Z-register.
Figure 4. The AT90S4414
Enhanced RISC Architecture
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 4
shows the AT90S4414
Enhanced RISC microcontrol-
ler architecture.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a two stage pipeline. While
one instruction is being executed, the next instruction is
pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system In-System Programma-
ble Flash memory.
With the relative jump and call instructions, the whole 2K
address space is directly accessed. Most
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 256 bytes data SRAM can be easily accessed through
the five different addressing modes supported in the
The memory spaces in the
architecture are all linear
and regular memory maps.
Figure 5. Memory Maps
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address the higher prior-
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