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Datasheet: 90S2343 (ATMEL Corporation)

8-bit Microcontroller With 2k Bytes Of In-system Programmable Flash

 

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ATMEL Corporation
1
Features
·
Utilizes the
AVR
®
Enhanced RISC Architecture
·
AVR - High Performance and Low Power RISC Architecture
·
118 Powerful Instructions - Most Single Clock Cycle Execution
·
2K bytes of In-System Programmable ISP Flash
­ SPI Serial Interface for In-System Programming
­ Endurance: 1,000 Write/Erase Cycles
·
128 bytes EEPROM
­ Endurance: 100,000 Write/Erase Cycles
·
128 bytes Internal RAM
·
32 x 8 General Purpose Working Registers
­ 3 AT90S/LS2323 Programmable I/O Lines
­ 5 AT90S/LS2343 Programmable I/O Lines
·
V
CC
: 4.0 - 6.0V AT90S2323/AT90S2343
·
V
CC
: 2.7 - 6.0V AT90LS2323/AT90LS2343
·
Power-On Reset Circuit
·
Speed Grades: 0 - 10 MHz AT90S2323/AT90S2343
·
Speed Grades: 0 - 4 MHz AT90LS2323/AT90LS2343
·
Up to 10 MIPS Throughput at 10 MHz
·
One 8-Bit Timer/Counter with Separate Prescaler
·
External and Internal Interrupt Sources
·
Programmable Watchdog Timer with On-Chip Oscillator
·
Low Power Idle and Power Down Modes
·
Programming Lock for Flash Program and EEPROM Data Security
·
Selectable On-Chip RC Oscillator
·
8-Pin Device
Description
The AT90S/LS2323 and AT90S/LS2343 is a low-power CMOS 8-bit microcontrollers
based on the
AVR
®
enhanced RISC architecture. By executing powerful instructions
in a single clock cycle, the AT90S/LS2323 and AT90S/LS2343 achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Rev. 1004AS­05/98
8-Bit
Microcontroller
with 2K Bytes of
In-System
Programmable
Flash
AT90S2323
AT90LS2323
AT90S2343
AT90LS2343
Preliminary
AT90S/LS2323
Pin Configuration
PDIP/SOIC
AT90S/LS2343
AT90S/LS2323
1
2
3
4
8
7
6
5
RESET
XTAL1
XTAL2
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
1
2
3
4
8
7
6
5
RESET
(CLOCK) PB3
PB4
GND
VCC
PB2 (SCK/T0)
PB1 (MISO/INT0)
PB0 (MOSI)
Note: This is a summary document. For the complete 34 page
document, please visit our website at
www.atmel.com
or e-mail at
literature@atmel.com
and request literature #1004A.
2
AT90S/LS2323 and AT90S/LS2343
Block Diagram
Figure 1. The AT90S/LS2343 Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PB0 - PB4
RESET
VCC
GND
CONTROL
LINES
8-BIT DATA BUS
3
AT90S/LS2323 and AT90S/LS2343
Figure 2. The AT90S/LS2323 Block Diagram
Description
The AT90S/LS2323 and AT90S/LS2343 provides the fol-
lowing features: 2K bytes of In-System Programmable
F l a s h , 1 2 8 b y t e s E E P R O M , 1 2 8 b y t e s S R A M , 3
(AT90S/LS2323) / 5 (AT90S/LS2343) general purpose I/O
lines, 32 general purpose working registers, an 8-bit
timer/counter, internal and external interrupts, programma-
ble Watchdog Timer with internal oscillator, an SPI serial
port for Flash Memory downloading and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
The device is manufactured using Atmel's high density
non-volatile memory technology. The on-chip Flash allows
the program memory to be reprogrammed in-system
through an SPI serial interface. By combining an 8-bit RISC
CPU with ISP Flash on a monolithic chip, the Atmel
AT90S/LS2323 and AT90S/LS2343 is a powerful micro-
controller that provides a highly flexible and cost effective
solution to many embedded control applications.
The AT90S/LS2323 and AT90S/LS2343 AVR is supported
with a full suite of program and system development tools
including: C compilers, macro assemblers, program debug-
ger/simulators, in-circuit emulators, and evaluation kits.
Comparison Between AT90S/LS2323
and AT90S/LS2343
The AT90S/LS2323 is intended for use with external quartz
crystal or ceramic resonator as the clock source. The star-
tup time is fuse selectable as either 1 ms (suitable for
ceramic resonator) or 16 ms (suitable for crystal). The
device has three I/0 pins.
The AT90S/LS2343 is intended for use with either an exter-
nal clock source or the internal RC oscillator as clock
source. The device has five I/0 pins.
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA REGISTER
PORTB
PROGRAMMING
LOGIC
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVERS
PB0 - PB2
RESET
VCC
GND
CONTROL
LINES
8-BIT DATA BUS
4
AT90S/LS2323 and AT90S/LS2343
Table 1 summarizes the differences in features of the two
devices.
Pin Descriptions AT90S/LS2323
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB2..PB0)
Port B is a 3-bit bi-directional I/O port. Port pins can provide
internal pull-up resistors (selected for each bit).
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Pin Descriptions AT90S/LS2343
VCC
Supply voltage pin.
GND
Ground pin.
Port B (PB4..PB0)
Port B is a 5-bit bi-directional I/O port. Port pins can provide
internal pull-up resistors (selected for each bit). When the
device is clocked from an external clock source, PB3 is
used as the clock input.
RESET
Reset input. A low on this pin for two machine cycles while
the oscillator is running resets the device.
CLOCK
Clock signal input in external clock mode.
Clock Sources
The AT90S/LS2323 contains an inverting amplifier which
can be configured for use as an on-chip oscillator, as
shown in Figure 3. XTAL1 and XTAL2 are input and output
respectively. Either a quartz crystal or a ceramic resonator
may be used. It is recommended to use the AT90S/LS2343
if an external clock source is used, since this gives an extra
I/O pin.
The AT90S/LS2343 can be clocked by an external clock
signal, as shown in Figure 4, or by the on-chip RC oscilla-
tor. This RC oscillator runs at a nominal frequency of 1
MHz (VCC = 5V). A fuse bit - RCEN - in the Flash memory
selects the on-chip RC oscillator as the clock source when
programmed ('0'). The AT90S/LS2343 is shipped with this
bit programmed.
Figure 3. Oscillator Connection
Figure 4. External Clock Drive Configuration
Table 1. Feature Difference Summary
Part
AT90S/LS2323
AT90S/LS2343
On-chip oscillator
amplifier
yes
no
Internal RC Clock
no
yes
PB3 usable
never
internal clock mode
PB4 usable
never
always
Startup time
1 ms / 16 ms
16
µ
s fixed
5
AT90S/LS2323 and AT90S/LS2343
AT90S/LS2323 and AT90S/LS2343
Architectural Overview
The fast-access register file concept contains 32 x 8-bit
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
Six of the 32 registers can be used as three 16-bits indirect
address register pointers for Data Space addressing-
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bit X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 5
shows the AT90S/LS2323 and AT90S/LS2343
AVR
Enhanced RISC microcontroller architecture.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
The
AVR
has Harvard architecture - with separate memo-
ries and buses for program and data. The program memory
is accessed with a two stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from
the program memory. This concept enables instructions to
be executed in every clock cycle. The program memory is
in-system downloadable Flash memory.
With the relative jump and call instructions, the whole 1K
address space is directly accessed. Most
AVR
instructions
have a single 16-bit word format. Every program memory
address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 8-bit stack pointer SP is read/write
accessible in the I/O space.
The 128 bytes data SRAM + register file and I/O registers
can be easily accessed through the five different address-
ing modes supported in the
AVR
architecture.
The memory spaces in the
AVR
architecture are all linear
and regular memory maps.
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