Endurance: 1,000 Write/Erase Cycles
5 AT90S/LS2343 Programmable I/O Lines
based on the
approaching 1 MIPS per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
with 2K Bytes of
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lowing features: 2K bytes of In-System Programmable
F l a s h , 1 2 8 b y t e s E E P R O M , 1 2 8 b y t e s S R A M , 3
(AT90S/LS2323) / 5 (AT90S/LS2343) general purpose I/O
lines, 32 general purpose working registers, an 8-bit
timer/counter, internal and external interrupts, programma-
ble Watchdog Timer with internal oscillator, an SPI serial
port for Flash Memory downloading and two software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The power
down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset.
non-volatile memory technology. The on-chip Flash allows
the program memory to be reprogrammed in-system
through an SPI serial interface. By combining an 8-bit RISC
CPU with ISP Flash on a monolithic chip, the Atmel
AT90S/LS2323 and AT90S/LS2343 is a powerful micro-
solution to many embedded control applications.
with a full suite of program and system development tools
including: C compilers, macro assemblers, program debug-
ger/simulators, in-circuit emulators, and evaluation kits.
crystal or ceramic resonator as the clock source. The star-
tup time is fuse selectable as either 1 ms (suitable for
ceramic resonator) or 16 ms (suitable for crystal). The
device has three I/0 pins.
nal clock source or the internal RC oscillator as clock
source. The device has five I/0 pins.
internal pull-up resistors (selected for each bit).
the oscillator is running resets the device.
internal clock operating circuit.
internal pull-up resistors (selected for each bit). When the
device is clocked from an external clock source, PB3 is
used as the clock input.
the oscillator is running resets the device.
can be configured for use as an on-chip oscillator, as
shown in Figure 3. XTAL1 and XTAL2 are input and output
respectively. Either a quartz crystal or a ceramic resonator
may be used. It is recommended to use the AT90S/LS2343
if an external clock source is used, since this gives an extra
signal, as shown in Figure 4, or by the on-chip RC oscilla-
tor. This RC oscillator runs at a nominal frequency of 1
MHz (VCC = 5V). A fuse bit - RCEN - in the Flash memory
selects the on-chip RC oscillator as the clock source when
programmed ('0'). The AT90S/LS2343 is shipped with this
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
address register pointers for Data Space addressing-
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bit X-register, Y-register and Z-register.
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 5
shows the AT90S/LS2323 and AT90S/LS2343
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
peripheral functions as Control Registers, Timer/Counters,
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
is accessed with a two stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from
the program memory. This concept enables instructions to
be executed in every clock cycle. The program memory is
in-system downloadable Flash memory.
address space is directly accessed. Most
address contains a 16- or 32-bit instruction.
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 8-bit stack pointer SP is read/write
accessible in the I/O space.
can be easily accessed through the five different address-
ing modes supported in the