Endurance: 1,000 Write/Erase Cycles
0 - 4 MHz, 2.7 - 6.0V
and Compare and Capture Modes
enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90S2313 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed
in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
with 2K bytes
datasheet, please visit our web site at
of In-System Programmable Flash, 128 bytes EEPROM,
128 bytes SRAM, 15 general purpose I/O lines, 32 general
purpose working registers, flexible timer/counters with
compare modes, internal and external interrupts, a pro-
grammable serial UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port for Flash Memory
downloading and two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the
SRAM, timer/counters, SPI port and interrupt system to
continue functioning. The power down mode saves the reg-
ister contents but freezes the oscillator, disabling all other
chip functions until the next interrupt or hardware reset.
non-volatile memory technology. The on-chip In-System
reprogrammed in-system through an SPI serial interface or
by a conventional nonvolatile memory programmer. By
combining an enhanced RISC 8-bit CPU with In-System
Programmable Flash on a monolithic chip, the Atmel
AT90S2313 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embed-
ded control applications.
gram and system development tools including: C compil-
ers, macro assemblers, program debugger/simulators, in-
circuit emulators, and evaluation kits.
vide internal pull-up resistors (selected for each bit). PB0
and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the on-chip analog
comparator. The Port B output buffers can sink 20mA and
can drive LED displays directly. When pins PB0 to PB7 are
used as inputs and are externally pulled low, they will
source current if the internal pull-up resistors are activated.
of the AT90S2313 as listed on page 38.
resistors, PD6..PD0. The Port D output buffers can sink 20
mA. As inputs, Port D pins that are externally pulled low will
source current if the pull-up resistors are activated.
of the AT90S2313 as listed on page 43.
the oscillator is running resets the device.
internal clock operating circuit.
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
general purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
address register pointers for Data Space addressing -
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bits X-register, Y-register and Z-register.
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 4
shows the AT90S2313 AVR Enhanced RISC microcontrol-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses ($00 -
$1F), allowing them to be accessed as though they were
ordinary memory locations.
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O memory
following those of the register file, $20 - $5F.
ries and buses for program and data. The program memory
is accessed with a two stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from
the program memory. This concept enables instructions to
be executed in every clock cycle. The program memory is
In-system Programmable Flash memory.
address space is directly accessed. Most
address contains a 16- or 32-bit instruction.
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 8-bit stack pointer SP is read/write
accessible in the I/O space.
can be easily accessed through the five different address-
ing modes supported in the AVR architecture.
and regular memory maps.