- Pin Configuration
- Architectural Overview
- General Purpose Register File
- ALU … Arithmetic Logic Unit
- In-System Programmable Flash Program Memory
- Program and Data Addressing Modes
- Subroutine and Interrupt Hardware Stack
- EEPROM Data Memory
- Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Sleep Modes
- Watchdog Timer
- EEPROM Read/Write Access
- Analog Comparator
- I/O Ports
- Port B
- Port D
- Memory Programming
- Program and Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Programming the Flash and EEPROM
- Parallel Programming
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Characteristics
- Electrical Characteristics
- Typical Characteristics
- AT90S1200 Register Summary
- Instruction Set Summary
- Ordering Information(1)
- Packaging Information
- Table of Contents
32 x 8 General Purpose Working Registers
Up to 12 MIPS Throughput at 12 MHz
On-chip Analog Comparator
Programmable Watchdog Timer with On-chip Oscillator
SPI Serial Interface for In-System Programming
External and Internal Interrupt Sources
Selectable On-chip RC Oscillator for Zero External Components
Fully Static Operation
Idle Mode: 0.4 mA
Power-down Mode: <1 µA
20-pin PDIP, SOIC and SSOP
4.0 - 6.0V (AT90S1200-12)
0 - 12 MHz, (AT90S1200-12)
with 1K Byte
architecture. By executing powerful instructions in a single clock cycle, the AT90S1200
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
isters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
assembler code programs. The AT90S1200 provides the following features: 1K byte of
In-System Programmable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32
general purpose working registers, internal and external interrupts, programmable
watchdog timer with internal oscillator, an SPI serial port for program downloading and
two software selectable power-saving modes. The Idle Mode stops the CPU while allow-
functioning. The Power-down mode saves the register contents but freezes the Oscilla-
tor, disabling all other chip functions until the next External Interrupt or hardware Reset.
The On-chip In-System Programmable Flash allows the program memory to be repro-
grammed in-system through an SPI serial interface or by a conventional nonvolatile
memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Pro-
grammable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful
microcontroller that provides a highly flexible and cost-effective solution to many embed-
ded control applications.
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
(selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the
negative input (AIN1), respectively, of the On-chip Analog Comparator. The Port B out-
put buffers can sink 20 mA and thus drive LED displays directly. When pins PB0 to PB7
are used as inputs and are externally pulled low, they will source current if the internal
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not active.
on page 30.
Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled
low will source current if the pull-up resistors are activated. The Port D pins are tri-stated
when a reset condition becomes active, even if the clock is not active.
on page 34.
clock is not running. Shorter pulses are not guaranteed to generate a reset.
be configured for use as an On-chip Oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the device from an external clock
source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.
connected as indicated in the figure.
MCU clock source. If enabled, the AT90S1200 can operate with no external compo-
nents. A control bit (RCEN) in the Flash Memory selects the On-chip RC Oscillator as
the clock source when programmed ("0"). The AT90S1200 is normally shipped with this
bit unprogram med ("1"). Parts with this bit progra mmed can be ord ered as
AT90S1200A. The RCEN-bit can be changed by parallel programming only. When
using the On-chip RC Oscillator for Serial Program downloading, the RCEN bit must be
programmed in Parallel Programming mode first.
ters with a single clock cycle access time. This means that during one single clock cycle,
one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from
the register file, the operation is executed, and the result is stored back in the register
file in one clock cycle.
stant and a register. Single register operations are also executed in the ALU. Figure 4
shows the AT90S1200 AVR RISC microcontroller architecture. The AVR uses a Har-
vard architecture concept with separate memories and buses for program and data
memories. The program memory is accessed with a 2-stage pipeline. While one instruc-
tion is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program
memory is In-System Programmable Flash memory.
directly accessed. All AVR instructions have a single 16-bit word format, meaning that
every program memory address contains a single 16-bit instruction.