- Block Diagram
- Pin Configuration
- Pin Description
- Electrical Characteristics
- AC Parameters
- AC Test Conditions
- AC Read Characteristics
- Timing Waveform of Read Cycle number 1, Either Side(4)
- Timing Waveform of Read Cycle number 2, Either Side (1)
- Timing Waveform of Read Cycle number 3, Either Side (1)(3)(4)(5)
- AC Write Characteristics
- Timing Waveform of Write Cycle number 1, R/W Controlled Timing (1) (2) (3) (7)
- Timing Waveform of Write Cycle number 2, CS Controlled Timing (1) (2) (3) (5)
- AC Busy Characteristics
- Timing Waveform of Read with BUSY (2) (3) (4) (For Master 67025)
- Timing Waveform of Write with Port-to-Port (1) (2) (3) (For Slave 67025 Only)
- Timing Waveform of Write with BUSY (For Slave 67025)
- Timing Waveform of Contention Cycle number 1, CS Arbitration (For Master 67025 only)
- Timing Waveform of Contention Cycle number 2, Address Valid Arbitration (For Master 67025 only)(1)
- AC Interrupt Characteristics
- Ordering Information
- Package Drawings
More Than One Device
M/S = L for Busy Input Flag On Slave
MASTER/SLAVE dual port approach in memory system applications results in full
speed, error free operation without the need of an additional discrete logic.
address and I/O pins that permit independent, asynchronous access for reads and
writes to any location in the memory. An automatic power down feature controlled by
CS permits the on-chip circuitry of each port in order to enter a very low stand by
extremely low standby supply current (typ = 1.0 µA) with a fast access time at 30 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 5 µW.
ability the M67025E is processed according to the methods of the latest revision of the
MIL PRF 38635 (Q and V) and/or ESA SCC 9000.
8 Kb x 16
Dual Port RAM
2. LB = Lower Byte UB = Upper Byte
independent read/write access to any memory location. These devices have an auto-
matic power-down feature controlled by CS. CS controls on-chip power-down circuitry
which causes the port concerned to go into stand-by mode when not selected (CS high).
When a port is selected access to the full memory array is permitted. Each port has its
own Output Enable control (OE). In read mode, the port's OE turns the Output drivers on
when set LOW. Non-conflicting READ/WRITE conditions are illustrated in Table 1.
chooses to use the interrupt function, a memory location (mail box or message center) is
assigned to each port. The left port interrupt flag (INT
location 1FFE. Similarly, the right port interrupt flag (INT
order to clear the interrupt flag (INT
reserved for mail boxes but become part of the RAM. See Table 3 for the interrupt
imum of 5 ns determine which port has access. In all cases, an active BUSY flag will be
set for the inhibited port.
simultaneously. Should this conflict arise, on-chip arbitration logic will determine which
port has access and set the BUSY flag for the inhibited port. BUSY is set at speeds that
allow the processor to hold the operation with its associated address and data. It should
be noted that the operation is invalid for the port for which BUSY is set LOW. The inhib-
ited port will be given access when BUSY goes inactive.
cide. The on-chip arbitration determines access in these circumstances. Two modes of
arbitration are provided: (1) if the addresses match and are valid before CS on-chip con-
trol logic arbitrates between CS
access (refer to Table 4). The inhibited port's BUSY flag is set and will reset when the
port granted access completes its operation in both arbitration modes.
several chips may be active simultaneously. If every chips has a hardware arbitrator,
and the addresses for each arrive at the same time one chip may activate in L BUSY
signal while another activates its R BUSY signal. Both sides are now busy and the
CPUs will wait indefinitely for their port to become free.
system which uses a single hardware arbitrator located on the MASTER. The SLAVE has
BUSY inputs which allow direct interface to the MASTER with no external components, giving a
speed advantage over other systems.
from writing until after the BUSY input has settled. Otherwise, the SLAVE chip may begin a
write cycle during a conflict situation. Conversely, the write pulse must extend a hold time
beyond BUSY to ensure that a write cycle occurs once the conflict is resolved. This timing is
inherent in all dual-port memory systems where more than one chip is active at the same time.
time. If a conflict then occurs, the write to the SLAVE will be inhibited because of the
MASTER's BUSY signal.
left or right side of the dual-port RAM to claim priority over the other for functions defined by the
system software. For example, the semaphore flag can be used by one processor to inhibit the
other from accessing a portion of the dual-port RAM or any other shared resource.
dent of each another. This means that the activity on the left port cannot slow the access
time of the right port. The ports are identical in function to standard CMOS static RAMs
and can be read from, or written to, at the same time with the only possible conflict aris-
ing from simultaneous writing to, or a simultaneous READ/WRITE operation on, a non-
semaphore location. Semaphores are protected against such ambiguous situations and
may be used by the system program to prevent conflicts in the non-semaphore segment
of the dual-port RAM. The devices have an automatic power-down feature controlled by
CS, the dual-port RAM select and SEM, the semaphore enable. The CS and SEM pins control
on-chip-power-down circuitry that permits the port concerned to go into stand-by mode when
not selected. This conditions is shown in Table 1 where CS and SEM are both high.
trollers and are typically very high-speed, software controlled or software-intensive
systems. These systems can benefit from the performance enhancement offered by the
M67025 hardware semaphores, which provide a lock-out mechanism without the need
for complex programming.
ity by permitting shared resources to be allocated in varying configurations. The
M67025E does not use its semaphore flags to control any resources through hardware,
thus allowing the system designer total flexibility in system architecture.
arbitration is that neither processor ever incurs wait states. This can prove to be a con-
siderable advantage in very high speed systems.
latches can be used to pass a flag or token, from one port to the other to indicate that a
shared resource is in use. The semaphore provides the hardware context for the "Token
Passing Allocation' method of use assignment. This method uses the state of a sema-
phore latch as a token indicating that a shared resource is in use. If the left processor
needs to use a resource, it requests the token by setting the latch. The processor then
verifies that the latch has been set by reading it. If the latch has been set the processor
assumes control over the shared resource. If the latch has not been set, the left proces-
sor has established that the right processor had set the latch first, has the token and is
using the shared resource. The left processor may then either repeatedly query the sta-
tus of the semaphore, or abandon its request for the token and perform another
operation whilst occasionally attempting to gain control of the token through a set and
test operation. Once the right side has relinquished the token the left side will be able to
take control of the shared resource.
phore latch, and is relinquished again when the same side writes a one to the latch.