(128K x 8)
- 5V Reprogramming
Memories. Their 1-megabit of memory is organized as 131,072 words by 8 bits. Manu-
factured with Atmel's advanced nonvolatile CMOS technology, the devices offer ac-
cess times to 45 ns (HF version) with a power dissipation of just 165 mW over the
commercial temperature range. When the device is deselected, the CMOS standby
current is less than 100
quire high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is
similar to reading from an EPROM. Reprogramming the AT49F010/HF010 is per-
formed by erasing the entire 1 megabit of memory and then programming on a byte
by byte basis. The byte programming time is a fast 50
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the ad-
dress pins is asserted on the outputs. The outputs are put
in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in prevent-
ing bus contention.
128K bytes memory array (or 120K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical "1". The entire device can be
erased at one time by using a 6-byte software code. The
chip erase code consists of 6-byte load commands to spe-
cific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).
ternally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is t
erased, the device is programmed (to a logical "0") on a
byte-by-byte basis. Please note that a data "0" cannot be
programmed back to a "1"; only erase operations can con-
vert "0"s to "1"s. Programming is accomplished via the in-
ternal device command register and is a 4 bus cycle op-
eration (please refer to the Command Definitions table).
The device will automatically generate the required inter-
nal program pulses.
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles.
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
indicate the end of a program cycle.
vice has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 8K bytes. This block, re-
ferred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea-
ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block's usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series of six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica-
tion code should be used to return to standard operation.
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
with Respect to Ground .............-0.6V to V
with Respect to Ground ................... -0.6V to +13.5V
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
or Software Product Identification. The manufacturer and
device code is the same for both modes.
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
AT49F010/HF010 provides another method for determin-
ing the end of a program or erase cycle. During a program
or erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e
AT49F010/HF010 in the following ways: (a) V
high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
5. See details under Software Product Identification Entry/Exit.
CE or Address,
whichever occurred first