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Datasheet: 29C516E (ATMEL Corporation)

16 Bit Flow Through Edac Error Detection and Correction Unit

 

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ATMEL Corporation

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29C516E
1
Atmel Corporation
Rev. D
(09 Dec. 97)
1. Introduction
The 29C516E
Atmel EDAC is a very low power
flow­through 16­bit Error Detection And Correction unit
(EDAC) with two user data buses. The EDAC is used in
a high integrity system for monitoring and correction of
data values coming from the memory space. During a
processor write cycle, at each memory location (16­bit
width), EDAC calculated checkword (6 or 8­bit width) is
added. When performing a read operation from memory,
the 29C516E verifies the entire checkword and data
combination. It detects and can correct 100% of all the
single­bit errors and it detects all double­bit errors.
When the 29C516E uses 6­checkbit, it can detect any
error on any single 4­bit memory chip. The 8­check­bit
option gives the additional capability to detect all errors
on any single 8­bit memory chip. All the errors are
signaled to the master system (via 2 error Flags) in order
to allow the processor to make the required action.
The 29C516E operates in two possible modes: corrected
or detected mode. In the corrected mode, the single­bit in
error is complemented (corrected). Then, the available
entire data is placed on the output port and the Correctable
Error Flag is set. In case of double­bit errors (or more),
the corrupted data is placed on the output port and the
Uncorrectable Error Flag is set. Note that when there is
more than two errors, then some bit patterns may appear
as possible correctable errors. Therefore, if the
environment produces this type of error, the EDAC must
be used in detect and provide no automatic correction.
Data and syndrome analysis must be done.
The 29C516E acts as a data buffer for
µ
P­memory
interfacing. A flow­through EDAC is placed in the data
bus path, between the processor and the memory to be
protected. This component is able to serve two different
users of one memory space. So, it forms the interface
between the 22/24­bit (16+6/16+8) memory data bus and
the two 16­bit processor data busses with a high drive
capability (­12.8 mA). The two data ports can be used to
create a dual port bus in front of memory space. The
User­1(2) can transfer data from/to the memory or
from/to the User­2(1), by­passing the memory. During
read or write memory cycles processed by the User­1(2),
the User­2(1) have the possibility to listen the
transferred data.
2. Features
D
Very Low Power CMOS
D
16­Bit operation with 6 or 8 Check Bits
D
Fast Error Detection : 31 ns (max.)
D
Fast Error Correction : 32 ns (max.)
D
Corrects all Single­Bit Errors
D
Detects all Double­Bit Errors
D
Detects some Multi­Bit Errors
D
Detects Chip Errors (x1, x4 & x8 RAM Format)
D
Correctable and Uncorrectable Error Flags
D
Two User Data Buses
D
User to User Transfer and Listening operation
D
High Drive Capability on Buses : ­12.8 mA
D
TTL Compatible
D
Single 5V
±
10% Power Supply
D
100 Pin Multilayer Quad Flat Pack
(Flat leaded or L leaded).
16­Bit Flow­Through EDAC
Error Detection And Correction unit
29C516E
2
Rev. D (09 Dec. 97)
3. Interface
3.1. Functional Diagram
Figure 1.Functional Diagram
BUFFER
BUFFER
RD/WR2
RD/WR1
CHECK BIT
SYNCHK
MEM2
I/O
EN1
MEM1
N22
DECODER
NCERR
SYNDROME
BUFFER
8
GENERATOR
I/O
8
MC[0..7]
CORRECT
MD[0..15]
CERR
SYNDROME
GENERATOR
EN2
BUFFER
U1D[0..15]
U2D[0..15]
I/O
I/O
TRANS
U2/U1
CONTROLLER
29C516E
16
8
16
16
16
16
8
16
16
16
16
16
16
3.2. Block Diagram
Figure 2.Block Diagram
MEM1
RD/WR1
MD[0..15]
MEM2
CERR
NCERR
RD/WR2
EN2
CORRECT
SYNCHK
N22
U1/U2
TRANS
U1D[0..15]
EN1
U2D[0..15]
MC[0..7]
VCC
GND
29C516E
29C516E
3
Rev. D
(09 Dec. 97)
3.3. Pin Configuration for multilayer quad Flat­pack (flat or L leaded)
Figure 3.Pin Configuration
2
3
1
U2D[15]
U1D[15]
N22
24
index corner
Gnd
75
30
27
25
51
26
16
Vcc
U2D[4]
U2D[6]
U2D[5]
12
Gnd
11
14
62
MD[4]
Vcc
MD[3]
U2D[7]
MD[6]
65
MQFPF100
or
MQFPL100
(Top view)
MD[7]
66
Gnd
15
60
61
10
U2D[8]
4
6
5
8
7
9
13
18
17
20
19
22
21
23
53
52
55
54
57
56
59
58
63
64
67
69
68
71
70
73
72
74
U2D[14]
U2D[13]
U2D[12]
U2D[11]
U2D[10]
U2D[9]
U2D[3]
U2D[2]
U2D[1]
U2D[0]
Vcc
Gnd
NCERR
CERR
U1D[0]
Vcc
EN1
RD/WR1
MEM1
Gnd
MD[0]
MD[1]
MD[2]
MD[5]
MD[8]
MD[9]
MD[10]
MD[11]
Vcc
MD[12]
MD[13]
MD[14]
MD[15]
28
29
76
77
78
79
80
nc
nc
MEM2
nc
nc
Gnd
nc
nc
nc
nc
Vcc
RD/WR2
CORRECT
SYNCHK
TRANS
U2/U1
EN2
Gnd
Gnd
MC[7]
MC[6]
MC[5]
MC[4]
Vcc
MC[3]
MC[2]
MC[1]
MC[0]
nc
nc
nc
Vcc
U1D[14]
U1D[13]
U1D[12]
Gnd
U1D[1
1]
U1D[10]
U1D[9]
U1D[8]
Vcc
U1D[7]
U1D[6]
U1D[5]
U1D[4]
Gnd
U1D[3]
U1D[2]
U1D[1]
nc
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
29C516E
4
Rev. D (09 Dec. 97)
3.4. Pin Description
Table 1:
Name
Pin Description
I/O
Active
Description
Buses
U1D
[
0..15
]
53,49..47,45..42,40..37,35..33,28
I/O*
High
User 1 Data Bus
U2D
[
0..15
]
23..20,18..15,13..10,8..5
I/O*
High
User 2 Data Bus
D
[
0..15
]
59..62,64..67,69..72,74..77
I/O*
High
Memory Data Bus
C
[
0..7
]
83..86,88..91
I/O*
High
Memory Check­bit Bus
Error Flags
CERR
26
O
Low
Correctable Error
NCERR
25
O
Low
Uncorrectable Error
General Control Signals
CORRECT
98
I*
High
When active, the EDAC is in CORRECT mode. If low,
the EDAC is in DETECT mode.
SYNCHK
97
I*
Low
Selects the Syndrome bits (high byte) and the Check­bits
(low byte) to be driven on the selected User Data Bus.
N22
27
I*
High
When active, the EDAC uses 6 check­bits. If low, the
EDAC uses 8 check­bits in memory read.
TRANS
96
I*
H/L
Selects the Data path to be used. If high, the EDAC
access the memory, if low, the EDAC access the transfer
buffer.
U2/U1
95
I*
H/L
Selects who is the master of User 1 and User 2. The
master is responsible for applying RD/WRx, MEMx, and
ENx signals in a correct way.
User 1 Control Signals
RD/WRT
55
I*
H/L
User 1 Read/Write signal
EN1
56
I*
Low
User 1 Output Enable
MEM1
57
I*
Low
User 1 Memory Select
User 1 Control Signals
RD/WR2
99
I*
H/L
User 2 Read/Write signal
EN2
94
I*
Low
User 2 Output Enable
MEM2
3
I*
Low
User 2 Memory Select
Power (Buffers)
VCC
B
9,19,32,41,54,63,73,87
I
­
Buffers supply (5 V nominal)
GND
B
4,14,24,36,46,58,68,78,92
I
­
Buffers 0 V nominal reference
Power (Core)
VCC
C
100
I
­
Core supply (5 V nominal)
GND
C
93
I
­
Core 0 V reference
* Pull­up buffers
29C516E
5
Rev. D
(09 Dec. 97)
4. Check­Bit Generation
The Check­bit Generator produces 8 check­bits
(whatever N22 value) from the incoming User Data Word
UxD[0..15] according the Table 2.
Example: to create check­bit 0, bit 13, 12, 8, 7, 6, 5, 4 and
0 of the Data Word are XORed together.
If memory devices 8­bit wide are used, 24 bits
(MD[0..15] & MC[0..7]) are stored to give error
detection. But if memory devices 1­bit or 4­bit wide are
used, 22 bits (MD[0..15] & MC[0..5]) are stored to give
error detection.
Table 2: Check Bit Generation (indicates a bit of UxD bus used in the XOR/NXOR)
MC
[
..
]
PARITY
UxD
[
..
]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
Even(XOR)
x
x
x
x
x
x
x
x
1
Even(XOR)
x
x
x
x
x
x
x
x
2
Odd(NXOR)
x
x
x
x
x
x
x
x
3
Odd(NXOR)
x
x
x
x
x
x
x
x
4
Even(XOR)
x
x
x
x
x
x
x
x
5
Even(XOR)
x
x
x
x
x
x
x
x
6
Even(XOR)
x
x
x
x
x
x
x
x
7
Odd(NXOR)
x
x
x
x
x
x
x
x
5. Syndrome Generation
The syndrome Generator produces 8 syndrome­bits
(whatever N22 value) from the incoming Memory Data
Word MD[0..15] and the associated Check­bits MC[0..7]
(or MC[0..5]) according the Table 3.
Syndrome­bit SY[x] is the XOR of the generated
Check­bit MC[x] with the generation of Chek­bit on
MD[..].
Example: to create syndrome­bit 3, first the bit 14,
13, 10, 4, 3, 2, 1 and 0 of the Data Word
(MD[14,13,10,4,3,2,1,0]) are NXORed. Then, the result
is XORed with the associated Check­bit (MC[3]) of the
Check­byte read in the same time as Data Word is
checked.
If the memory uses x8 devices, then the bits should be
physically divided as follows: MC[0..7], MD[0..7] and
MD[8..15] . For x4 organization, the bits should be
divided MC[0..2]+MC[6], MC[3..5]+MC[7], MD[0..3],
MD[4..7], MD[8..11] and MD[12..15].
Table 3: Syndrome Bit Generation (indicates a bit of MD and MC buses used in the XOR/NXOR)
SY
[
..
]
PARITY
MD
[
..
]
MC
[
..
]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
7
5
4
3
6
2
1
0
0
EVEN(XOR)
x
x
x
x
x
x
x
x
x
1
EVEN(XOR)
x
x
x
x
x
x
x
x
x
2
ODD(NXOR)
x
x
x
x
x
x
x
x
x
3
ODD(NXOR)
x
x
x
x
x
x
x
x
x
4
EVEN(XOR)
x
x
x
x
x
x
x
x
x
5
EVEN(XOR)
x
x
x
x
x
x
x
x
x
6
EVEN(XOR)
x
x
x
x
x
x
x
x
x
7
ODD(NXOR)
x
x
x
x
x
x
x
x
x
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