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Datasheet: 29C512 (ATMEL Corporation)

512k 64k X 8 5-volt Only Cmos Flash Memory

 

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ATMEL Corporation

Document Outline

Features
·
Fast Read Access Time ­ 70 ns
·
5-volt Only Reprogramming
·
Sector Program Operation
­ Single Cycle Reprogram (Erase and Program)
­ 512 Sectors (128 Bytes/Sector)
­ Internal Address and Data Latches for 128 Bytes
·
Internal Program Control and Timer
·
Hardware and Software Data Protection
·
Fast Sector Program Cycle Time ­ 10 ms
·
DATA Polling for End of Program Detection
·
Low Power Dissipation
­ 50 mA Active Current
­ 100 µA CMOS Standby Current
·
Typical Endurance > 10,000 Cycles
·
Single 5V ± 10% Supply
·
CMOS and TTL Compatible Inputs and Outputs
·
Commercial and Industrial Temperature Ranges
·
Green (Pb/Halide-free) Packaging Option
1.
Description
The AT29C512 is a 5-volt only in-system Flash programmable and erasable read only
memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Man-
ufactured with Atmel's advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 100
µA. The device endurance is such that any sector can typically be written to
in excess of 10,000 times.
To allow for simple in-system reprogrammability, the AT29C512 does not require high
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from an EPROM.
Reprogramming the AT29C512 is performed on a sector basis; 128 bytes of data are
loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 128 bytes of data are internally
latched, freeing the address and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the sector and then program
the latched data using an internal control timer. The end of a program cycle can be
detected by DATA polling of I/O7. Once the end of a program cycle has been
detected, a new access for a read or program can begin.
512K (64K x 8)
5-volt Only
Flash Memory
AT29C512
0456H­FLASH­2/05
2
0456H­FLASH­2/05
AT29C512
2.
Pin Configurations
2.1
32-lead PLCC Top View
2.2
32-lead TSOP (Type 1) Top View
Pin Name
Function
A0 - A15
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A12
A15
NC
NC
VCC
WE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
3
0456H­FLASH­2/05
AT29C512
3.
Block Diagram
4.
Device Operation
4.1
Read
The AT29C512 is accessed like an EPROM. When CE and OE are low and WE is high, the data
stored at the memory location determined by the address pins is asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
4.2
Byte Load
Byte loads are used to enter the 128 bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a low pulse on the WE or CE input with
CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or
WE, whichever occurs last. The data is latched by the first rising edge of CE or WE.
4.3
Program
The device is reprogrammed on a sector basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device. Any byte that is not loaded during the
programming of its sector will be indeterminate. Once the bytes of a sector are loaded into the
device, they are simultaneously programmed during the internal programming period. After the
first data byte has been loaded into the device, successive bytes are entered in the same man-
ner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within
150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transi-
tion is not detected within 150 µs of the last low-to-high transition, the load period will end and
the internal programming period will start. A7 to A15 specify the sector address. The sector
address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the
byte address within the sector. The bytes may be loaded in any order; sequential loading is not
required. Once a programming operation has been initiated, and for the duration of t
WC
, a read
operation will effectively be a polling operation.
4
0456H­FLASH­2/05
AT29C512
4.4
Software Data Protection
A software controlled data protection feature is available on the AT29C512. Once the software
protection is enabled a software algorithm must be issued to the device before a program may
be performed. The software protection feature may be enabled or disabled by the user; when
shipped from Atmel, the software data protection feature is disabled. To enable the software
data protection, a series of three program commands to specific addresses with specific data
must be performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software program
commands must obey the sector program timing specifications. Once set, the software data pro-
tection feature remains active unless its disable command is issued. Power transitions will not
reset the software data protection feature; however, the software feature will guard against inad-
vertent program cycles during power transitions.
Once set, software data protection will remain active unless the disable command sequence is
issued.
After setting SDP, any attempt to write to the device without the 3-byte command sequence will
start the internal write timers. No data will be written to the device; however, for the duration of
t
WC
, a read operation will effectively be a polling operation.
After the software data protection's 3-byte command code is given, a byte load is performed by
applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by
the first rising edge of CE or WE. The 128 bytes of data must be loaded into each sector by the
same procedure as outlined in the program section under device operation.
4.5
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT29C512 in the following ways:
(a) V
CC
sense ­ if V
CC
is below 3.8V (typical), the program function is inhibited; (b) V
CC
power on
delay ­ once V
CC
has reached the V
CC
sense level, the device will automatically time out 5 ms
(typical) before programming; (c) Program inhibit ­ holding any one of OE low, CE high or WE
high inhibits program cycles; and (d) Noise filter ­ pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
4.6
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product. In
addition, users may wish to use the software product identification mode to identify the part (i.e.,
using the device code), and have the system software use the appropriate sector size for pro-
gram operations. In this manner, the user can have a common board design for 256K to 4-
megabit densities and, with each density's sector size in a memory map, have the system soft-
ware apply the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
5
0456H­FLASH­2/05
AT29C512
4.7
DATA Polling
The AT29C512 features DATA polling to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. DATA polling may begin at any time during the program cycle.
4.8
Toggle Bit
In addition to DATA polling the AT29C512 provides another method for determining the end of a
program or erase cycle. During a program or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin
at any time during a program cycle.
4.9
Optional Chip Erase Mode
The entire device can be erased by using a 6-byte software code. Please see Software Chip
Erase application note for details.
5.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55
°C to +125°C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65
°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
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