- Pin Configurations
- Block Diagram
- Device Operation
- Absolute Maximum Ratings*
- DC and AC Operating Range
- Operating Modes
- DC Characteristics
- AC Read Characteristics
- AC Read Waveforms(1)(2)(3)(4)
- Input Test Waveforms and Measurement Level
- Output Test Load
- Pin Capacitance
- AC Byte Load Characteristics
- AC Byte Load Waveforms
- Program Cycle Characteristics
- Program Cycle Waveforms(1)(2)(3)
- Software Data Protection Enable Algorithm(1)
- Software Data Protection Disable Algorithm(1)
- Software Protected Program Cycle Waveform(1)(2)(3)
- Data Polling Characteristics(1)
- Data Polling Waveforms
- Toggle Bit Characteristics(1)
- Toggle Bit Waveforms(1)(2)(3)
- Software Product Identification Entry(1)
- Software Product Identification Exit(1)
- Ordering Information
- Packaging Information
Internal Address and Data Latches for 64 Bytes
Chip Erase Time 10 ms
only memory (PEROM). Its 256K of memory is organized as 32,768 words by 8 bits.
Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers
access times to 70 ns with power dissipation of just 275 mW. When the device is
deselected, the CMOS standby current is less than 300 µA. The device endurance is
such that any sector can typically be written to in excess of 10,000 times.
input voltages for programming. Five-volt-only commands determine the operation of
the device. Reading data out of the device is similar to reading from a static RAM.
Reprogramming the AT29C256 is performed on a page basis; 64 bytes of data are
loaded into the device and then simultaneously programmed. The contents of the entire
device may be erased by using a six-byte software code (although erasure before pro-
gramming is not needed).
latched, freeing the address and data bus for other operations. Following the initiation of
a program cycle, the device will automatically erase the page and then program the
latched data using an internal control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle has been detected a new
access for a read, program or chip erase can begin.
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of
CE or WE. Byte loads are used to enter the 64 bytes of a page to be programmed or the
software codes for data protection and chip erasure.
that is not loaded during the programming of its page will be indeterminate. Once the
bytes of a page are loaded into the device, they are simultaneously programmed during
the internal programming period. After the first data byte has been loaded into the
device, successive bytes are entered in the same manner. Each new byte to be pro-
grammed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-
high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not
detected within 150 µs of the last low-to-high transition, the load period will end and the
internal programming period will start. A6 to A14 specify the page address. The page
address must be valid during each high-to-low transition of WE (or CE). A0 to A5 specify
the byte address within the page. The bytes may be loaded in any order; sequential
loading is not required. Once a programming operation has been initiated, and for the
duration of t
rithm must be issued to the device before a program may be performed. The software
protection feature may be enabled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable the software data protection,
a series of three program commands to specific addresses with specific data must be
performed. After the software data protection is enabled the same three program com-
mands must begin each program cycle in order for the programs to occur. All software
program commands must obey the page program timing specifications. Once set, the
software data protection feature remains active unless its disable command is issued.
Power transitions will not reset the software data protection feature, however the soft-
ware feature will guard against inadvertent program cycles during power transitions.
sequence is issued.
sequence will start the internal write timers. No data will be written to the device; how-
ever, for the duration of t
performed by applying a low pulse on the WE or CE input with CE or WE low (respec-
tively) and OE high. The address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or WE. The 64 bytes of
data must be loaded into each sector by the same procedure as outlined in the program
section under device operation.
inhibits program cycles; and (d) Noise filter pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
Operating Modes or Product Identification.
in the complement of the loaded data on I/O7. Once the program cycle has been com-
pleted, true data is valid on all outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
successive attempts to read data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid
data will be read. Examining the toggle bit may begin at any time during a program
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
with Respect to Ground ...................................-0.6V to +6.25V
with Respect to Ground .............................-0.6V to V
with Respect to Ground ...................................-0.6V to +13.5V
5. See details under Software Product Identification Entry/Exit.