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Datasheet: 29C020 (ATMEL Corporation)

2-megabit 256k X 8 5-volt Only Cmos Flash Memory

 

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ATMEL Corporation
2-Megabit
(256K x 8)
5-volt Only
CMOS Flash
Memory
AT29C020
Features
Fast Read Access Time - 90 ns
5-Volt-Only Reprogramming
Sector Program Operation
Single Cycle Reprogram (Erase and Program)
1024 Sectors (256 bytes/sector)
Internal Address and Data Latches for 256-Bytes
Internal Program Control and Timer
Hardware and Software Data Protection
Two 8 KB Boot Blocks with Lockout
Fast Sector Program Cycle Time - 10 ms
DATA Polling for End of Program Detection
Low Power Dissipation
40 mA Active Current
100
A CMOS Standby Current
Typical Endurance > 10,000 Cycles
Single 5V
10% Supply
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT29C020 is a 5-volt-only in-system Flash programmable and erasable read only
memory (PEROM). Its 2 megabits of memory is organized as 262,144 bytes. Manu-
factured with Atmel's advanced nonvolatile CMOS technology, the device offers ac-
cess times to 90 ns with power dissipation of just 220 mW over the commercial tem-
perature range. When the device is deselected, the CMOS standby current is less
than 100
A. Device endurance is such that any sector can typically be written to in
excess of 10,000 times.
(continued)
AT29C020
DIP Top View
TSOP Top View
Type 1
Pin Configurations
Pin Name
Function
A0 - A17
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
PLCC Top View
0291I/G20-I6/97
To allow for simple in-system reprogrammability, the
AT29C020 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the opera-
tion of the device. Reading data out of the device is similar
t o rea ding from an EPROM. Reprogramming the
AT29C020 is performed on a sector basis; 256-bytes of
data are loaded into the device and then simultaneously
programmed.
During a reprogram cycle, the address locations and 256-
bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation
of a program cycle, the device will automatically erase the
sector and then program the latched data using an internal
control timer. The end of a program cycle can be detected
by DATA polling of I/O7. Once the end of a program cycle
has been detected, a new access for a read or program
can begin.
Description (Continued)
Device Operation
READ: The AT29C020 is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-
line control gives designers flexibility in preventing bus
contention.
BYTE LOAD: Byte loads are used to enter the 256-
bytes of a sector to be programmed or the software codes
for data protection. A byte load is performed by applying a
low pulse on the WE or CE input with CE or WE low (re-
spectively) and OE high. The address is latched on the
falling edge of CE or WE, whichever occurs last. The data
is latched by the first rising edge of CE or WE.
PROGRAM: The device is reprogrammed on a sector
basis. If a byte of data within a sector is to be changed,
data for the entire sector must be loaded into the device.
Any byte that is not loaded during the programming of its
sector will be indeterminate. Once the bytes of a sector
are loaded into the device, they are simultaneously pro-
grammed during the internal programming period. After
the first data byte has been loaded into the device, suc-
cessive bytes are entered in the same manner. Each new
byte to be programmed must have its high to low transition
on WE (or CE) within 150
s of the low to high transition of
WE (or CE) of the preceding byte. If a high to low transition
is not detected within 150
s of the last low to high transi-
tion, the load period will end and the internal programming
(continued)
Block Diagram
period will start. A8 to A17 specify the sector address. The
sector address must be valid during each high to low tran-
sition of WE (or CE). A0 to A7 specify the byte address
within the sector. The bytes may be loaded in any order;
sequential loading is not required. Once a programming
operation has been initiated, and for the duration of t
WC
, a
read operation will effectively be a polling operation.
SOFTWARE DATA PROTECTION: A software control-
led data protection feature is available on the AT29C020.
Once the software protection is enabled a software algo-
rithm must be issued to the device before a program may
be performed. The software protection feature may be en-
abled or disabled by the user; when shipped from Atmel,
the software data protection feature is disabled. To enable
the software data protection, a series of three program
commands to specific addresses with specific data must
be performed. After the software data protection is en-
abled the same three program commands must begin
each program cycle in order for the programs to occur. All
software program commands must obey the sector pro-
gram timing specifications. Once set, the software data
protection feature remains active unless its disable com-
mand is issued. Power transitions will not reset the soft-
ware data protection feature, however the software fea-
ture will guard against inadvertent program cycles during
power transitions.
After setting SDP, any attempt to write to the device with-
out the 3-byte command sequence will start the internal
2
AT29C020
(continued)
Temperature Under Bias................. -55
C to +125
C
Storage Temperature...................... -65
C to +150
C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
write timers. No data will be written to the device; however,
for the duration of t
WC
, a read operation will effectively be
a polling operation.
After the software data protection's 3-byte command code
is given, a sector of data is loaded into the device using the
sector program timing specifications.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT29C020 in
the following ways: (a) V
CC
sense-- if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) V
CC
power
on delay-- once V
CC
has reached the V
CC
sense level,
the device will automatically time out 5 ms (typical) before
programming. (c) Program inhibit-- holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter-- pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
PRODUCT IDENTIFICATION: The product identifica-
tion mode identifies the device and manufacturer as At-
mel. It may be accessed by hardware or software opera-
tion. The hardware operation mode can be used by an ex-
ternal programmer to identify the correct programming al-
gorithm for the Atmel product. In addition, users may wish
to use the software product identification mode to identify
the part (i.e. using the device code), and have the system
software use the appropriate sector size for program op-
erations. In this manner, the user can have a common
board design for 256K to 4-megabit densities and, with
each density's sector size in a memory map, have the sys-
tem software apply the appropriate sector size.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT29C020 features DATA poll-
ing to indicate the end of a program cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
Device Operation (Continued)
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA p o l l i n g t h e
AT29C020 provides another method for determining the
end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
OPTIONAL CHIP ERASE MODE: The
entire
device
can be erased by using a 6-byte software code. Please
see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT: The
AT29C020 has two designated memory blocks that have
a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature
has been enabled. Each of these blocks consists of 8K
bytes; the programming lockout feature can be set inde-
pendently for either block. While the lockout feature does
not have to be activated, it can be activated for either or
both blocks.
These two 8K memory sections are referred to as
boot
blocks
. Secure code which will bring up a system can be
contained in a boot block. The AT29C020 blocks are lo-
cated in the first 8K bytes of memory and the last 8K bytes
of memory. The boot block programming lockout feature
can therefore support systems that boot from the lower
addresses of memory or the higher addresses. Once the
programming lockout feature has been activated, the data
in that block can no longer be erased or programmed;
data in other memory locations can still be changed
through the regular programming methods. To activate the
lockout feature, a series of seven program commands to
specific addresses with specific data must be performed.
Please see Boot Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on
either block, the chip erase function will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A
software
method is available to determine whether programming of
AT29C020
3
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
V
IL
V
IL
V
IH
Ai
D
OUT
Program
(2)
V
IL
V
IH
V
IL
Ai
D
IN
5V Chip Erase
V
IL
V
IH
V
IL
Ai
Standby/Write Inhibit
V
IH
X
(1)
X
X
High Z
Program Inhibit
X
X
V
IH
Program Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Product Identification
Hardware
V
IL
V
IL
V
IH
A1 - A17 = V
IL
, A9 = V
H
,
(3)
A0 = V
IL
Manufacturer Code
(4)
A1 - A17 = V
IL
, A9 = V
H
,
A0 = V
IH
Device Code
(4)
Software
(5)
A0 = V
IL
Manufacturer Code
(4)
A0 = V
IH
Device Code
(4)
4. Manufacturer Code: 1F, Device Code: DA
5. See details under Software Product Identification Entry/Exit.
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
3. V
H
= 12.0V
0.5V.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB1
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
Com.
100
A
Ind.
300
A
I
SB2
V
CC
Standby Current TTL
CE = 2.0V to V
CC
3
mA
I
CC
V
CC
Active Current
f = 5 MHz; I
OUT
= 0 mA
40
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
.45
V
V
OH1
Output High Voltage
I
OH
= -400
A
2.4
V
V
OH2
Output High Voltage CMOS
I
OH
= -100
A; V
CC
= 4.5V
4.2
V
DC and AC Operating Range
AT29C020-90
AT29C020-10
AT29C020-12
AT29C020-15
Operating
Temperature (Case)
Com.
0
C - 70
C
0
C - 70
C
0
C - 70
C
0
C - 70
C
Ind.
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
V
CC
Power Supply
5V
10%
5V
10%
5V
10%
5V
10%
either boot block section is locked out. See Software Prod-
uct Identification Entry and Exit sections. When the device
is in the software product identification mode, a read from
location 00002H will show if programming the lower ad-
dress boot block is locked out while reading location
FFFF2H will do so for the upper boot block. If the data is
FE, the corresponding block can be programmed; if the
data is FF, the program lockout feature has been activated
and the corresponding block cannot be programmed. The
software product identification exit mode should be used
to return to standard operation.
Device Operation (Continued)
4
AT29C020
AC Read Characteristics
AT29C020-90
AT29C020-10
AT29C020-12
AT29C020-15
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
t
ACC
Address to Output Delay
0
90
100
120
150
ns
t
CE
(1)
CE to Output Delay
90
100
120
150
ns
t
OE
(2)
OE to Output Delay
0
40
0
50
0
50
0
70
ns
t
DF
(3, 4)
CE or OE to Output Float
0
25
0
25
0
30
0
40
ns
t
OH
Output Hold from OE, CE or
Address, whichever
occurred first
0
0
0
0
ns
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
Output Test Load
Pin Capacitance
(f = 1 MHz, T = 25C)
(1)
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Note:
1. This parameter is characterized and is not 100% tested.
t
R
, t
F
< 5 ns
Note: While CE is active, any address inputs that cause V
IH
to drop
below 2.0V or V
IL
to rise above 0.8V for a duration of up to 15 ns
may cause the device to read incorrectly.
Input Test Waveforms and Measurement Level
AT29C020
5
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