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Datasheet: 28C64 (ATMEL Corporation)

64k 8k X 8 Cmos E2prom

 

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ATMEL Corporation
AT28C64/X
64K (8K x 8)
CMOS
E
2
PROM
Features
Fast Read Access Time - 120 ns
Fast Byte Write - 200
s or 1 ms
Self-Timed Byte Write Cycle
Internal Address and Data Latches
Internal Control Timer
Automatic Clear Before Write
Direct Microprocessor Control
READY/BUSY Open Drain Output
DATA Polling
Low Power
30 mA Active Current
100
A CMOS Standby Current
High Reliability
Endurance: 10
4
or 10
5
Cycles
Data Retention: 10 Years
5V
10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28C64 is a low-power, high-performance 8,192 words by 8 bit nonvolatile
Electrically Erasable and Programmable Read Only Memory with popular, easy to
use features. The device is manufactured with Atmel's reliable nonvolatile technol-
ogy.
(continued)
PDIP, SOIC
Top View
Pin Name
Function
A0 - A12
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
RDY/BUSY
Ready/Busy Output
NC
No Connect
DC
Don't Connect
Pin Configurations
TSOP
Top View
LCC, PLCC
Top View
Note: PLCC package pins 1 and
17 are DON'T CONNECT.
0001G
AT28C64/X
2-193
Description (Continued)
Block Diagram
The AT28C64 is accessed like a Static RAM for the read
or write cycles without the need for external components.
During a byte write, the address and data are latched in-
ternally, freeing the microprocessor address and data bus
for other operations. Following the initiation of a write cy-
cle, the device will go to a busy state and automatically
clear and write the latched data using an internal control
timer. The device includes two methods for detecting the
end of a write cycle, level detection of RDY/BUSY (unless
pin 1 is N.C.) and DATA POLLING of I/O
7
. Once the end
of a write cycle has been detected, a new access for a
read or write can begin.
The CMOS technology offers fast access times of 120 ns
at low power dissipation. When the chip is deselected the
standby current is less than 100
A.
Atmel's 28C64 has additional features to ensure high
quality and manufacturability. The device utilizes error cor-
rection internally for extended endurance and for im-
proved data retention characteristics. An extra 32-bytes of
E
2
PROM are available for device identification or tracking.
Temperature Under Bias................. -55C to +125C
Storage Temperature...................... -65C to +150C
All Input Voltages
(including NC Pins)
with Respect to Ground ................... -0.6V to +6.25V
All Output Voltages
with Respect to Ground .............-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ................... -0.6V to +13.5V
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions beyond those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Absolute Maximum Ratings*
2-194
AT28C64/X
Device Operation
READ: The AT28C64 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) initi-
ates a byte write. The address location is latched on the
falling edge of WE (or CE); the new data is latched on the
rising edge. Internally, the device performs a self-clear be-
fore write. Once a byte write has been started, it will auto-
matically time itself to completion. Once a programming
operation has been initiated and for the duration of t
WC
, a
read operation will effectively be a polling operation.
FAST BYTE WRITE: The AT28C64E offers a byte write
time of 200
s maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
READY/BUSY: Pin 1 is an open drain READY/BUSY
output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle
and is released at the completion of the write. The open
drain connection allows for OR-tying of several devices to
the same RDY/BUSY line. Pin 1 is not connected for the
AT28C64X.
DATA POLLING: The AT28C64 provides DATA POLL-
ING to signal the completion of a write cycle. During a
write cycle, an attempted read of the data being written
results in the complement of that data for I/O
7
(the other
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all outputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways. (a) V
CC
sense-- if V
CC
is below 3.8V (typical) the write function is
inhibited. (b) V
CC
power on delay-- once V
CC
h a s
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a byte write. (c) Write Inhibit--
holding any one of OE low, CE high or WE high inhibits
byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip
is cleared when a 10 msec low pulse is applied to WE.
DEVICE IDENTIFICATION: A n e x t r a 3 2 - b y t e s o f
E
2
PROM memory are available to the user for device
identification. By raising A9 to 12
0.5V and using ad-
dress locations 1FE0H to 1FFFH the additional bytes may
be written to or read from in the same manner as the regu-
lar memory array.
AT28C64/X
2-195
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
+ 1V
10
A
I
LO
Output Leakage Current
V
I/O
= 0V to V
CC
10
A
I
SB1
V
CC
Standby Current CMOS
CE = V
CC
- 0.3V to V
CC
+ 1.0V
100
A
I
SB2
V
CC
Standby Current TTL
CE = 2.0V to V
CC
+ 1.0V
Com.
2
mA
Ind.
3
mA
I
CC
V
CC
Active Current AC
f = 5 MHz; I
OUT
= 0 mA
CE = V
IL
Com.
30
mA
Ind.
45
mA
V
IL
Input Low Voltage
0.8
V
V
IH
Input High Voltage
2.0
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
= 4.0 mA for RDY/BUSY
.45
V
V
OH
Output High Voltage
I
OH
= -400
A
2.4
V
DC Characteristics
AT28C64-12
AT28C64-15
AT28C64-20
AT28C64-25
Operating
Temperature (Case)
Com.
0C - 70C
0C - 70C
0C - 70C
0C - 70C
Ind.
-40C - 85C
-40C - 85C
-40C - 85C
-40C - 85C
V
CC
Power Supply
5V
10%
5V
10%
5V
10%
5V
10%
DC and AC Operating Range
Mode
CE
OE
WE
I/O
Read
V
IL
V
IL
V
IH
D
OUT
Write
(2)
V
IL
V
IH
V
IL
D
IN
Standby/Write Inhibit
V
IH
X
(1)
X
High Z
Write Inhibit
X
X
V
IH
Write Inhibit
X
V
IL
X
Output Disable
X
V
IH
X
High Z
Chip Erase
V
IL
V
H
(3)
V
IL
High
Z
3. V
H
= 12.0V
0.5V.
Notes: 1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
Operating Modes
2-196
AT28C64/X
AT28C64-12
AT28C64-15
AT28C64-20
AT28C64-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
t
ACC
Address to Output Delay
120
150
200
250
ns
t
CE
(1)
CE to Output Delay
120
150
200
250
ns
t
OE
(2)
OE to Output Delay
10
60
10
70
10
80
10
100
ns
t
DF
(3, 4)
CE or OE High to Output
Float
0
45
0
50
0
55
0
60
ns
t
OH
Output Hold from OE, CE
or Address, whichever
occurred first
0
0
0
0
ns
AC Read Characteristics
Notes: 1. CE may be delayed up to t
ACC
- t
CE
after the address
transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling
edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first
(C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Waveforms
(1, 2, 3, 4)
t
R
, t
F
< 20 ns
Input Test Waveforms and
Measurement Level
Output Test Load
Typ
Max
Units
Conditions
C
IN
4
6
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Pin Capacitance (f = 1 MHz, T = 25C)
(1)
Note: 1. This parameter is characterized and is not 100% tested.
AT28C64/X
2-197
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