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Datasheet: 27C4096 (ATMEL Corporation)

4-megabit 256k X 16 Otp Eprom

 

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ATMEL Corporation
AT27C4096
1
Features
Fast Read Access Time - 55 ns
Low Power CMOS Operation
100
A Maximum Standby
40 mA Maximum Active at 5 MHz
JEDEC Standard Packages
40-Lead 600 mil PDIP
44-Lead PLCC
40-Lead TSOP (10 mm x 14 mm)
Direct Upgrade from 512K bit, 1M bit, and 2M bit
(AT27C516, AT27C1024, and AT27C2048) EPROMs
5V
10% Power Supply
High Reliability CMOS Technology
2,000V ESD Protection
200 mA Latchup Immunity
Rapid
TM
Programming Algorithm - 50
s/word (typical)
CMOS and TTL Compatible Inputs and Outputs
Integrated Product Identification Code
Commercial and Industrial Temperature Ranges
Description
The AT27C4096 is a low-power, high-performance 4,194,304-bit one-time program-
mable read only memory (OTP EPROM) organized 256K by 16 bits. It requires a sin-
gle 5V power supply in normal read mode operation. Any word can be accessed in
less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16
organization makes this part ideal for high-performance 16- and 32-bit microprocessor
systems.
TSOP Top View
Type 1
PDIP Top View
PLCC Top View
4-Megabit
(256K x 16)
OTP EPROM
AT27C4096
0311E-A06/97
Pin Configurations
Note:
Both GND pins must be
connected.
Pin Name
Function
A0 - A17
Addresses
O0 - O15
Outputs
CE
Chip Enable
OE
Output Enable
NC
No Connect
(continued)
AT27C4096
2
Description
In read mode, the AT27C4096 typically consumes 15 mA.
Standby mode supply current is typically less than 10
A
.
T h e A T 2 7 C 4 0 9 6 i s a va i l a b l e i n i n d u s t r y s t a n d a rd
JEDEC-approved one-time programmable (OTP) plastic
PDIP, PLCC, and TSOP packages. The device features
two-line control (CE, OE) to eliminate bus contention in
high-speed systems.
With high density 256K word storage capability, the
AT27C4096 allows firmware to be stored reliably and to be
accessed by the system without the delays of mass storage
media.
Atmel's AT27C4096 has additional features that ensure
high quality and efficient production use. The Rapid
TM
Pro-
gramming Algorithm reduces the time required to program
the part and guarantees reliable programming. Program-
ming time is typically only 50
s/word. The Integrated Prod-
uct Identification Code electronically identifies the device
and manufacturer. This feature is used by industry stan-
dard programming equipment to select the proper program-
ming algorithms and voltages.
System Considerations
Switching between active and standby conditions via the
Chip Enable pin may produce transient voltage excursions.
Unless accommodated by the system design, these tran-
sients may exceed data sheet limits, resulting in device
non-conformance. At a minimum, a 0.1
F high frequency,
low inherent inductance, ceramic capacitor should be uti-
lized for each device. This capacitor should be connected
between the V
CC
and Ground terminals of the device, as
close to the device as possible. Additionally, to stabilize the
supply voltage level on printed circuit boards with large
EPROM arrays, a 4.7
F bulk electrolytic capacitor should
be utilized, again connected between the V
CC
and Ground
terminals. This capacitor should be positioned as close as
possible to the point where the power supply is connected
to the array.
AT27C4096
3
Block Diagram
Operating Modes
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to the Programming characteristics.
3. V
H
= 12.0
0.5V.
4. Two identifier words may be selected. All Ai inputs are held low (V
IL
), except A9, which is set to V
H
, and A0, which is toggled
low (V
IL
) to select the Manufacturer's Identification word and high (V
IH
) to select the Device Code word.
5. Standby V
CC
current (I
SB
) is specified with V
PP
= V
CC
. V
CC
> V
PP
will cause a slight increase in I
SB
.
Mode/Pin
CE
OE
Ai
V
PP
Outputs
Read
V
IL
V
IL
Ai
X
(1)
D
OUT
Output Disable
X
V
IH
X
X
High Z
Standby
V
IH
X
X
X
(5)
High Z
Rapid Program
(2)
V
IL
V
IH
Ai
V
PP
D
IN
PGM Verify
V
IH
V
IL
Ai
V
PP
D
OUT
PGM Inhibit
V
IH
V
IH
X
V
PP
High Z
Product Identification
(4)
V
IL
V
IL
A9 = V
H
(3)
A0 = V
IH
or V
IL
A1 - A17 = V
IL
V
CC
Identification Code
Absolute Maximum Ratings*
Temperature Under Bias ...................... -55
C to +125
C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Maximum voltage is -0.6V dc which may undershoot
to -2.0V for pulses of less than 20 ns. Maximum out-
put pin voltage is V
CC
+ 0.75V dc which may over-
shoot to +7.0V for pulses of less than 20 ns.
Storage Temperature............................ -65
C to +150
C
Voltage on Any Pin with
Respect to Ground ...............................-2.0V to +7.0V
(1)
Voltage on A9 with
Respect to Ground ............................-2.0V to +14.0V
(1)
V
PP
Supply Voltage with
Respect to Ground .............................-2.0V to +14.0V
(1)
AT27C4096
4
DC and AC Operating Conditions for Read Operation
AT27C4096
-55
-70
-90
-12
-15
Operating Temperature
(Case)
Com.
0
C - 70
C
0
C - 70
C
0
C - 70
C
0
C - 70
C
0
C - 70
C
Ind.
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
-40
C - 85
C
V
CC
Power Supply
5V
10%
5V
10%
5V
10%
5V
10%
5V
10%
AC Characteristics for Read Operation
Note:
2, 3, 4, 5. See the AC Waveforms for Read Operation diagram.
AT27C4096
-55
-70
-90
-12
-15
Symbol
Parameter
Condition
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
t
ACC
(3)
Address to
Output Delay
CE = OE
= V
IL
55
70
90
120
150
ns
t
CE
(2)
CE to Output Delay
OE = V
IL
55
70
90
120
150
ns
t
OE
(2)(3)
OE to Output Delay
CE = V
IL
20
30
35
40
50
ns
t
DF
(4)(5)
OE or CE High to
Output Float,
whichever occurred
first
20
20
20
30
35
ns
t
OH
(4)
Output Hold from
Address, CE or OE,
whichever occurred
first
7
7
0
0
0
ns
DC and Operating Characteristics for Read Operation
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. V
PP
may be connected directly to V
CC
, except during programming. The supply current would then be the sum of I
CC
and
I
PP
.
Symbol
Parameter
Condition
Min
Max
Units
I
LI
Input Load Current
V
IN
= 0V to V
CC
1
A
I
LO
Output Leakage Current
V
OUT
= 0V to V
CC
5
A
I
PP1
(2)
V
PP
(1)
Read/Standby Current
V
PP
= V
CC
10
A
I
SB
V
CC
(1)
Standby Current
I
SB1
(CMOS)
CE = V
CC
0.3V
100
A
I
SB2
(TTL)
CE = 2.0 to V
CC
+ 0.5V
1
mA
I
CC
V
CC
Active Current
f = 5 MHz, I
OUT
= 0 mA,
CE = V
IL
40
mA
V
IL
Input Low Voltage
-0.6
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 2.1 mA
0.4
V
V
OH
Output High Voltage
I
OH
= -400
A
2.4
V
AT27C4096
5
AC Waveforms for Read Operation
(1)
Notes:
1.
Timing measurement references are 0.8V and 2.0V. Input AC drive levels are 0.45V and 2.4V, unless otherwise specified.
2.
OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
.
3.
OE may be delayed up to t
ACC
- t
OE
after the address is valid without impact on t
ACC
.
4.
This parameter is only sampled and is not 100% tested.
5.
Output float is defined as the point when data is no longer driven.
Input Test Waveforms and Measurement Levels
For -55 devices only:
t
R
, t
F
< 5 ns (10% to 90%)
For -70, -90, -12 and -15 devices:
t
R
, t
F
< 20 ns (10% to 90%)
Pin Capacitance
(f = 1 MHz T = 25C)
(1)
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Typ
Max
Units
Conditions
C
IN
4
10
pF
V
IN
= 0V
C
OUT
8
12
pF
V
OUT
= 0V
Output Test Load
Note:
CL = 100 pF including jig
capacitance, except for
the -45 and -55 devices,
where CL = 30 pF.
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