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Datasheet: Am79C972BKC (Advanced Micro Systems)

Pcnet(tm)-fast i i i Single-chip 10/100 MBPS Pci Ethernet Controller With Integrated PHY

 

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Publication# 21485
Rev: D Amendment/0
Issue Date: December 1999
Refer to AMD's Website (www.amd.com) for the latest information.
Am79C972
PCnetTM-FAST+
Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
DISTINCTIVE CHARACTERISTICS
n
Integrated Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) bus
-- 32-bit glueless PCI host interface
-- Supports PCI clock frequency from DC to
33 MHz independent of network clock
-- Supports network operation with PCI clock
from 15 MHz to 33 MHz
-- High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
-- PCI specification revision 2.1 compliant
-- Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
-- Supports both PCI 3.3-V and 5.0-V signaling
environments
-- Plug and Play compatible
-- Supports an unlimited PCI burst length
-- Big endian and little endian byte alignments
supported
-- Implements optional PCI power management
event (PME) pin
n
Media Independent Interface (MII) for
connecting external 10/100 megabit per second
(Mbps) transceivers
-- IEEE 802.3-compliant MII
-- Intelligent Auto-PollTM external PHY status
monitor and interrupt
-- Supports both auto-negotiable and non
auto-negotiable external PHYs
-- Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
n
Supports General Purpose Serial Interface
(GPSI) with receive frame tagging support for
internetworking applications
n
Full-duplex operation supported in MII and GPSI
ports with independent Transmit (TX) and
Receive (RX) channels
n
Supports PC97, PC98, and Net PC requirements
-- Implements full OnNow features including
pattern matching and link status wake-up
-- Implements Magic Packet mode
-- Magic Packet mode and the physical address
loaded from EEPROM at power up without
requiring PCI clock
-- Supports PCI Bus Power Management
Interface Specification Version 1.0
-- Supports Advanced Configuration and
Power Interface (ACPI) Specification
Version 1.0
-- Supports Network Device Class Power
Management Specification Version 1.0
n
Large independent internal TX and RX FIFOs
-- Programmable FIFO watermarks for both
transmit and receive operations
-- Receive frame queuing for high latency PCI
bus host operation
-- Programmable allocation of buffer space
between transmit and receive queues
n
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
n
EEPROM interface supports jumperless design
and provides through-chip programming
-- Supports full programmability of half-/full-
duplex operation for external 10/100 Mbps
PHYs through EEPROM mapping
-- Programmable PHY reset output pin capable
of resetting external PHY without needing
buffering
n
Integrated oscillator circuit eliminates need for
external crystal
n
Extensive programmable LED status support
n
Support for operation in industrial temperature
range (-40
C to +85C)
2
Am79C972
n
Supports up to 1 megabyte (Mbyte) optional
Boot PROM or Flash for diskless node
application
n
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame
n
Programmable Inter Packet Gap (IPG) to
address less network aggressive MAC
controllers
n
Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
n
IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
mode for board-level production connectivity
test
n
Software compatible with AMD PCnet Family
and LANCE/C-LANCE register and descriptor
architecture
n
Compatible with the existing PCnet Family
driver and diagnostic software
n
Available in 160-pin PQFP and 176-pin TQFP
packages
n
+3.3 V power supply with 5 V tolerant I/Os
enables broad system compatibility
n
Extensive programmable internal/external
loopback capabilities
n
Supports patented External Address Detection
Interface (EADI)
GENERAL DESCRIPTION
The Am79C972 PCnet-FAST+ controller is a highly-
integrated 32-bit full-duplex, 10/100-Megabit per sec-
ond (Mbps) Ethernet controller solution, designed to
address high-performance system application require-
ments. It is a flexible bus mastering device that can be
used in any application, including network-ready PCs
and bridge/router designs. The bus master architecture
provides high data throughput and low CPU and sys-
tem bus utilization. The Am79C972 controller is fabri-
cated with advanced low-power 3.3-V CMOS process
to provide low operating current for power sensitive ap-
plications.
The Am79C972 PCnet-FAST+ controller also has sev-
e ra l e n h a n c e m e n t s ove r i t s p r e d e c e s s o r, t h e
Am79C971 PCnet-FAST device. In addition to integrat-
ing the SRAM on chip, it further reduces system imple-
mentation cost by the addition of a new EEPROM
programmable pin (PHY_RST), an internal oscillator
circuit eliminating the need for an external crystal, and
the integration of the PAL function needed for Magic
Packet application. The PHY_RST pin is implemented
to reset the external PHY without increasing the load to
the PCI bus and to block RST to the PHY when PG
input is LOW.
The 32-bit multiplexed bus interface unit provides a di-
rect interface to the PCI local bus, simplifying the
design of an Ethernet node in a PC system. The
Am79C972 PCnet-FAST+ controller provides the com-
plete interface to an Expansion ROM or Flash device
allowing add-on card designs with only a single load
per PCI bus interface pin. With its built-in support for
both little and big endian byte alignment, this controller
also addresses non-PC applications. The Am79C972
controller's advanced CMOS design allows the bus in-
terface to be connected to either a +5-V or a +3.3-V sig-
naling environment. A compliant IEEE 1149.1 JTAG
test interface for board-level testing is also provided, as
well as a NAND tree test structure for those systems
that cannot support the JTAG interface.
The Am79C972 PCnet-FAST+ controller is also com-
pliant with the PC97, PC98, and Net PC specifications.
It includes the full implementation of the Microsoft
OnNow and ACPI specifications, which are backward
compatible with the Magic Packet technology, and is
compliant with the PCI Bus Power Management Inter-
face Specification by supporting the four power man-
agement states (D0, D1, D2, and D3), the optional
PME pin, and the necessary configuration and data
registers.
The Am79C972 PCnet-FAST+ controller is ideally
suited for Network PC (Net PC), motherboard, network
interface card (NIC), and embedded designs. It is avail-
able in a 160-pin Plastic Quad Flat Pack (PQFP) pack-
age and also in a 176-pin Thin Quad Flat Pack (TQFP)
package for form factor sensitive designs.
The Am79C972 PCnet-FAST+ controller is a complete
Ethernet node integrated into a single VLSI device. It
contains a bus interface unit, a Direct Memory Access
(DMA) Buffer Management Unit, an ISO/IEC 8802-3
(IEEE 802.3)-compliant Media Access Controller
(MAC), a large Transmit FIFO and a large Receive
FIFO, and an IEEE 802.3-compliant MII. Both IEEE
802.3 compliant full-duplex and half-duplex operations
are supported on the MII and GPSI interfaces. 10/100
Mbps operation is supported through the MII.
The Am79C972 PCnet-FAST+ controller is register
compatible with the LANCETM (Am7990) and C-
LANCETM (Am79C90) Ethernet controllers, and all
Ethernet controllers in the PCnet Family except
ILACCTM (Am79C900), including the PCnet-ISATM con-
troller (Am79C960), PCnet-ISA+TM (Am79C961),
Am79C972
3
P C n e t - I S A I I TM ( A m 7 9 C 9 6 1 A ) , P C n e t - 3 2 TM
( A m 7 9 C 9 6 5 ) , P C n e t - P C I TM ( A m 7 9 C 9 7 0 ) ,
PCnet-PCI IITM (Am79C970A), and the PCnet-FASTTM
(Am79C971). The Buffer Management Unit supports
the LANCE and PCnet descriptor software models.
The Am79C972 PCnet-FAST+ controller supports
auto-configuration in the PCI configuration space.
Additional Am79C972 controller configuration parame-
ters, including the unique IEEE physical address, can
b e re ad f ro m a n ext e r n al n onvo l a ti l e m e m o r y
(EEPROM) immediately following system reset.
In addition, the device provides programmable on-chip
LED drivers for transmit, receive, collision, link integrity,
Magic Packet status, activity, address match, full-du-
plex, or 100 Mbps status. The Am79C972 controller
also provides an EADI to allow external hardware ad-
dress filtering in internetworking applications and a re-
ceive frame tagging feature.
The Am79C972 PCnet-FAST+ controller contains
12-kilobyte (Kbyte) buffers, the largest of its class of 10/
100 Mbps Ethernet controllers. The large internal
buffer is programmable between the transmit (TX) and
receive (RX) queues for optimal performance.
With the rise of embedded networking applications op-
erating in harsh environments where temperatures
may exceed the normal commercial temperature win-
dow (0C to 70C), an industrial temperature (-40C to
+85C) version is available in both the 160-pin PQFP
and the 176-pin TQFP package. The Am79C972
PCnet-FAST+ 10/100 Mbps Ethernet controller can be
designed with the industrial temperature capable
Am79C874 NetPHY-1LP 10/100 Mbps Ethernet PHY
for a complete and robust Fast Ethernet solution that
can withstand extreme temperature environments.
4
Am79C972
BLOCK DIAGRAM
CLK
RST
AD[31:0]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
PCI Bus
Interface
Unit
Buffer
Management
Unit
Expansion Bus
Interface
Bus
Rcv
FIFO
Bus
Xmt
FIFO
FIFO
Control
Network
Port
Manager
MAC
Rcv
FIFO
12K
SRAM
MAC
Xmt
FIFO
JTAG
Port
Control
OnNow
Power
Management
Unit
802.3
MAC
Core
GPSI
Port
MII
Port
EADI
Port
93C46
EEPROM
Interface
LED
Control
EBUA_EBA[7:0]
EBDA[15:8]
EBD[7:0]
EROMCS
AS_EBOE
EBWE
EBCLK
TXEN
TXCLK
TXDAT
RXEN
RXCLK
RXDAT
CLSN
TBC_IN
TBC_EN
EECS
EESK
EEDI
EEDO
LED0
LED1
LED2
LED3
PME
RWU
WUMI
PG
TCK
TMS
TDI
TDO
PHY_RST
TX_ER
TXD[3:0]
TX_EN
TX_CLK
COL
RXD[3:0]
RX_ER
RX_CLK
RX_DV
CRS
MDC
MDIO
SRDCLK
SRD
SFBD
EAR
MIIRXFRTGD/RXFRTGD
MIIRXFRTGE/RXFRTGE
21485C-1
Am79C972
5
TABLE OF CONTENTS
AM79C972 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
DISTINCTIVE CHARACTERISTICS1
GENERAL DESCRIPTION2
BLOCK DIAGRAM4
TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
CONNECTION DIAGRAM (PQR160)8
CONNECTION DIAGRAM (PQL176)9
PIN DESIGNATIONS (PQR160) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
PIN DESIGNATIONS (PQL176) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PIN DESIGNATIONS (PQR160, PQL176). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PIN DESIGNATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Listed By Driver Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Board Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BASIC FUNCTIONS26
System Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DETAILED FUNCTIONS27
Slave Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave Configuration Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Slave I/O Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Master Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Software Interrupt Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Transmit Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Loopback Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
General Purpose Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Media Independent Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Automatic Network Port Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
External Address Detection Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Expansion Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
LED Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Magic Packet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
IEEE 1149.1 (1990) Test Access Port Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
NAND Tree Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
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