HTML datasheet archive (search documentation on electronic components) Search datasheet (1.687.043 components)
Search field

Datasheet: AM79C971 (Advanced Micro Systems)

Pcnet(tm)-fast i i i Single-chip 10/100 MBPS Pci Ethernet Controller With Integrated PHY

 

Download: PDF   ZIP
 

Document Outline

Publication# 20550
Rev: E Amendment: /0
Issue Date: May 2000
Am79C971
PCnetTM-FAST
Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
DISTINCTIVE CHARACTERISTICS
s
Single-chip Fast Ethernet controller for the
Peripheral Component Interconnect (PCI) local
bus
-- 32-bit glueless PCI host interface
-- Supports PCI clock frequency from DC to
33 MHz independent of network clock
-- Supports network operation with PCI clock
from 15 MHz to 33 MHz
-- High performance bus mastering
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
-- PCI specification revision 2.1 compliant
-- Supports PCI Subsystem/Subvendor ID/
Vendor ID programming through the
EEPROM interface
-- Supports both PCI 5.0-V and 3.3-V signaling
environments
-- Plug and Play compatible
-- Supports an unlimited PCI burst length
-- Big endian and little endian byte alignments
supported
s
Integrated 10BASE-T and 10BASE-2/5 (AUI)
Physical Layer Interface
-- Single-chip IEEE/ANSI 802.3, IEC/ISO 8802-3
and Blue Book Ethernet-compliant solution
-- Automatic Twisted-Pair receive polarity
detection and correction
-- Internal 10BASE-T transceiver with Smart
Squelch to Twisted-Pair medium
-- IEEE 802.3-compliant auto-negotiable
10BASE-T interface
s
Supports General Purpose Serial Interface
(GPSI)
s
Media Independent Interface (MII) for
connecting external 10- or 100-Megabit per
second (Mbps) transceivers
-- IEEE 802.3-compliant MII
-- Intelligent Auto-PollTM external PHY status
monitor and interrupt
-- Includes intelligent on-chip Network Port
Manager that provides auto-port selection
between MII, on-chip 10BASE-T port, and AUI
without software support
-- Supports both auto-negotiable and non
auto-negotiable external PHYs
-- Supports 10BASE-T, 100BASE-TX/FX,
100BASE-T4, and 100BASE-T2 IEEE 802.3-
compliant MII PHYs at full- or half-duplex
s
Internal/external loopback capabilities on all
ports
s
Supports patented External Address Detection
Interface (EADI)
-- Receive frame tagging support for inter-
networking applications
s
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
s
Full-duplex operation supported in AUI,
10BASE-T, MII, and GPSI ports with
independent Transmit (TX) and Receive (RX)
channels
s
Flexible buffer architecture
-- Large independent internal TX and RX FIFOs
-- SRAM-based FIFO buffer extension
supporting up to 128 kilobytes (Kbytes)
-- 1/2 Gigabit per second (Gbps) internal data
bandwidth
-- Programmable FIFO watermarks for both TX
and RX operations
-- RX frame queuing for high latency PCI bus
host operation
-- Programmable allocation of buffer space
between RX and TX queues
s
EEPROM interface supports jumperless design
and provides through-chip programming
-- Supports full programmability of half-/full-
duplex operation for external 100 Mbps PHYs
through EEPROM mapping
s
Extensive LED status support
2
Am79C971
s
Supports up to 1 Megabyte (Mbyte) optional
Boot PROM and Flash for diskless node
application
s
Look-Ahead Packet Processing (LAPP) data
handling technique reduces system overhead
by allowing protocol analysis to begin before
the end of a receive frame
s
Includes Programmable Inter Packet Gap (IPG)
to address less network aggressive MAC
controllers
s
Offers the Modified Back-Off algorithm to
address the Ethernet Capture Effect
s
IEEE 1149.1-compliant JTAG Boundary Scan
test access port interface and NAND tree test
mode for board-level production connectivity
test
s
Implements low-power management for critical
battery powered application and green PCs
-- Includes two power-saving sleep modes
(sleep and snooze)
-- Integrated Magic PacketTM technology
support for remote power of networked PCs
s
Software compatible with AMD PCnet Family
and LANCE/C-LANCE register and descriptor
architecture
s
Compatible with the existing PCnet Family
driver/diagnostic software
s
Available in 160-pin TQFP and 176-pin TQFP
packages
GENERAL DESCRIPTION
The Am79C971 controller is a single-chip 32-bit full-du-
plex, 10/100-Megabit per second (Mbps) highly-
integrated Ethernet system solution, designed to
address high-performance system application require-
ments. It is a flexible bus mastering device that can be
used in any application, including network-ready PCs
and bridge/router designs. The bus master architecture
provides high data throughput in the system and low
CPU and system bus utilization. The Am79C971 con-
troller is fabricated with AMD's advanced low-power
Complementary Metal Oxide Semiconductor (CMOS)
process to provide low operating and standby current
for power sensitive applications.
The Am79C971 controller is a complete Ethernet node
integrated into a single VLSI device. It contains a bus
interface unit, a Direct Memory Access (DMA) Buffer
Management Unit, an ISO/IEC 8802-3 (IEEE 802.3)-
compliant Media Access Controller (MAC), a large
Transmit FIFO and a large Receive FIFO, SRAM-
based FIFO extension with support for up to 128K
bytes of external frame buffering, an IEEE 802.3u-com-
pliant MII, an IEEE 802.3-compliant Twisted-Pair Trans-
ceiver Media Attachment Unit (10BASE-T MAU), and
an IEEE 802.3-compliant Attachment Unit Interface
(AUI). Both proprietary full-duplex and IEEE 802.3
compliant half-duplex operation are supported on the
MII, AUI, GPSI, and 10BASE-T MAU interfaces. 10-
Mbps operation is supported through the MII, AUI, and
10BASE-T MAU interfaces, and 100 Mbps operation is
supported through the MII. The 10BASE-T MAU inter-
face includes an IEEE 802.3-compliant auto-negotia-
tion implementation, which will automatically negotiate
between half- and full-duplex with another IEEE 802.3-
compliant auto-negotiation 10BASE-T device.
The Am79C971 controller is register compatible with
the LANCE (Am7990) Ethernet controller, the C-
LANCE (Am79C90) Ethernet controller, and all Ether-
net controllers in the PCnet Family except ILACC
(Am79C900), including the PCnet-ISA controller
(Am79C960),PCnet-ISA+ controller (Am79C961),
PCnet-ISA II controller (Am79C961A), PCnet-32 con-
t r o l l e r ( A m 7 9 C 9 6 5 ) , P C n e t - P C I c o n t r o l l e r
( A m 7 9 C 9 7 0 ) , a n d P C n e t - P C I I I c o n t r o l l e r
(Am79C970A). The Buffer Management Unit supports
the LANCE and PCnet descriptor software models.
The 32-bit multiplexed bus interface unit provides a
direct interface to the PCI local bus, simplifying the
design of an Ethernet node in a PC system. The
Am79C971 controller provides the complete interface
to an Expansion ROM or Flash device allowing add-on
card designs with only a single load per PCI bus inter-
face pin. With its built-in support for both little and big
endian byte alignment, this controller also addresses
non-PC applications. The Am79C971 controller's ad-
vanced CMOS design allows the bus interface to be
connected to either a +5-V or a +3.3-V signaling envi-
ronment. A compliant IEEE 1149.1 JTAG test interface
for board-level testing is also provided, as well as a
NAND tree test structure for those systems that cannot
support the JTAG interface.
The Am79C971 controller supports auto-configuration
in the PCI configuration space. Additional Am79C971
controller configuration parameters, including the
unique IEEE physical address, can be read from an ex-
ternal non-volatile memory (EEPROM) immediately fol-
lowing system reset.
The integrated Manchester encoder/decoder (MEN-
DEC) eliminates the need for an external Serial Inter-
face Adapter (SIA) in the system. The built-in GPSI
allows the MENDEC to be bypassed.
Am79C971
3
In addition, the device provides programmable on-chip
LED drivers for transmit, receive, collision, receive po-
larity, link integrity, activity, link active, address match,
full-duplex, MII select, 100 Mbps, or jabber status. The
Am79C971 controller also provides an EADI to allow
external hardware address filtering in internetworking
applications and a receive frame tagging feature.
For power sensitive applications where low standby
current is desired, the device incorporates two sleep
functions to reduce overall system power consumption,
excellent for notebooks and green PCs. In conjunction
with these low power modes, the PCnet-FAST control-
ler also has integrated functions to support Magic
Packet technology, an inexpensive technology that al-
lows remote wake up of networked PCs.
The controller has the capability to automatically select
either the MII, AUI, or Twisted-Pair transceiver. Only
one interface is active at any one time. Any of the net-
work interfaces can be programmed to operate in either
half-duplex or full-duplex mode (AUI full-duplex only
supports the 10BASE-F standard).
The dual Transmit and Receive FIFOs optimize system
overhead, providing sufficient latency tolerance at 10
Mbps and for 100-Mbps systems where low latencies
can be guaranteed during frame transmission and
reception.
In highly loaded 10-Mbps systems, such as servers or
when using the controller in a 100-Mbps environment,
the additional frame buffering capability provided by a
16-bit wide SRAM interface provides high performance
and high latency tolerance on the system bus and net-
work.
The Am79C971 controller can use up to 128 Kbytes of
SRAM as an extension of its dual Transmit and Receive
FIFOs. When no SRAM is used, the Am79C971 con-
troller's FIFOs are programmed to bypass the SRAM
interface.
IMPORTANT NOTE: A "No SRAM configuration" is only
valid for 10Mb mode. In 100Mb mode, SRAM is man-
datory and must always be used.
ISO/IEC 8802-3 and IEEE 802.3 will be used inter-
changeably when referring to half-duplex 10 Mbps net-
works. IEEE 802.3 or IEEE 802.3u will be used
interchangeably only when referring to half-duplex 100-
Mbps Ethernet networks, since the IEEE standard is
not ISO approved yet. Full-duplex is a proprietary stan-
dard and is not approved by IEEE or ISO.
4
Am79C971
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.
Am79C971
TEMPERATURE RANGE
C = Commercial (0
C to +70
C)
SPEED OPTION
PACKAGE TYPE
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Not applicable
K = Plastic Quad Flat Pack (PQR160)
V = Thin Quad Flat Pack (PQL176)
Am79C971
Single-Chip Full-Duplex 10/100 Mbps Ethernet
Controller for PCI Local Bus
Valid Combinations
Am79C971
KC\W,
VC\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
\W
C
K\V
Am79C971
5
BLOCK DIAGRAM
FIFO
Control
PCI Bus
Interface
Unit
XTAL1
XTAL2
RXD[3:0]
RX_ER
RX_CLK
RX_DV
CRS
MDC
MDIO
MII
Port
JTAG
Port
Control
SRDCLK
SRD
EAR
EADI
Port
SF/BD
TXD+/-
RXD+/-
LED3
10BASE-T
MAU
DO+/-
DI+/-
CI+/-
Manchester
Encoder/
Decoder
(PLS) &
AUI Port
802.3
MAC
Core
LED0
LED1
LED2
LED
Control
EECS
EESK
EEDI
EEDO
93C46
EEPROM
Interface
TCK
TMS
TDO
TDI
Buffer
Management
Unit
COL
TXD[3:0]
TX_EN
TX_E
TX_CLK
Expansion Bus Interface
EBUA_EBA[7:0]
EBDA[15:8]
EBD[7:0]
EROMCS
ERAMCS
AS_EBOE
EBWE
EBCLK
Bus
Rcv
FIFO
MAC
Rcv
FIFO
Bus
Xmt
FIFO
MAC
Xmt
FIFO
TXP+/-
CLK
RST
AD[31:00]
C/BE[3:0]
PAR
FRAME
TRDY
IRDY
STOP
IDSEL
DEVSEL
REQ
GNT
PERR
SERR
INTA
SLEEP
TXEN
TXCLK
TXDAT
RXEN
RXCLK
RXDAT
CLSN
GPSI
Port
RXFRTGE/MIIRXFRTGE
RXFRTGD/MIIRXFRTGD
Auto
Negotiation
Network
Port
Manager
20550D-1
© 2019 • ICSheet
Contact form
Main page