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Datasheet: 29LV160B (Advanced Micro Devices)

16 Megabit (2 M X 8-bit/1 M X 16-bit) Cmos 3.0 Volt-only Boot Sector Flash Memory

 

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Advanced Micro Devices

Document Outline

PRELIMINARY
Publication# 21358
Rev: F Amendment/+2
Issue Date: March 1998
Am29LV160B
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
-- Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
-- Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
s
Manufactured on 0.35 m process technology
s
Supports Common Flash Memory Interface
(CFI)
s
High performance
-- Full voltage range: access times as fast as 90 ns
-- Regulated voltage range: access times as fast
as 80 ns
s
Ultra low power consumption (typical values at
5 MHz)
-- 200 nA Automatic Sleep mode current
-- 200 nA standby mode current
-- 9 mA read current
-- 20 mA program/erase current
s
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
-- One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
-- Supports full chip erase
-- Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Unlock Bypass Program Command
-- Reduces overall programming time when
issuing multiple program command sequences
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 1,000,000 write cycle guarantee per
sector
s
Package option
-- 48-ball FBGA
-- 48-pin TSOP
-- 44-pin SO
s
CFI (Common Flash Interface) compliant
-- Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
s
Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power supply Flash
-- Superior inadvertent write protection
s
Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
s
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting
program or erase cycle completion (not
available on 44-pin SO)
s
Erase Suspend/Erase Resume
-- Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data
P R E L I M I N A R Y
2
Am29LV160B
GENERAL DESCRIPTION
The Am29LV160B is a 16 Mbit, 3.0 Volt-only Flash memory
organized as 2,097,152 bytes or 1,048,576 words. The
device is offered in 48-ball FBGA, 44-pin SO, and 48-pin
TSOP packages. The word-wide data (x16) appears on
DQ15DQ0; the byte-wide (x8) data appears on DQ7DQ0.
This device is designed to be programmed in-system with
the standard system 3.0 volt V
CC
supply. A 12.0 V V
PP
or 5.0
V
CC
are not required for write or erase operations. The
d e vi ce ca n a l so b e pro g r am m e d i n st a nd a r d
EPROM programmers.
The device offers access times of 80, 90, and 120 ns,
allowing high speed microprocessors to operate
without wait states. To eliminate bus contention the
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
The device requires only a single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The Am29LV160B is entirely command set compatible
w it h t h e J E D E C s i n g l e - p ow e r-s u p p ly F l a s h
standard
. Commands are written to the command reg-
ister using standard microprocessor write timings. Reg-
ister contents serve as input to an internal state-
machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase opera-
tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program
algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically pre-
programs the array (if it is not already programmed) be-
fore executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array
data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low V
CC
detector that automatically inhibits write operations dur-
ing power transitions. The hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode
. Power consumption is greatly reduced in both
these modes.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
P R E L I M I N A R Y
Am29LV160B
3
PRODUCT SELECTOR GUIDE
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
Family Part Number
Am29LV160B
Speed Option
Regulated Voltage Range: V
CC
=3.03.6 V
80R
Full Voltage Range: V
CC
= 2.73.6 V
90
120
Max access time, ns (t
ACC
)
80
90
120
Max CE# access time, ns (t
CE
)
80
90
120
Max OE# access time, ns (t
OE
)
30
35
50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Ad
dre
ss Lat
ch
A0A19
21358F-1
P R E L I M I N A R Y
4
Am29LV160B
CONNECTION DIAGRAMS
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
21358F-2
Reverse TSOP
Standard TSOP
P R E L I M I N A R Y
Am29LV160B
5
CONNECTION DIAGRAMS
Special Handling Instructions
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150
C for prolonged periods of time.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
21358F-3
A1
B1
C1
D1
E1
F1
G1
H1
A2
B2
C2
D2
E2
F2
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
A4
B4
C4
D4
E4
F4
G4
H4
A5
B5
C5
D5
E5
F5
G5
H5
A6
B6
C6
D6
E6
F6
G6
H6
DQ15/A-1
V
SS
BYTE#
A16
A15
A14
A12
A13
DQ13
DQ6
DQ14
DQ7
A11
A10
A8
A9
V
CC
DQ4
DQ12
DQ5
A19
NC
RESET#
WE#
DQ11
DQ3
DQ10
DQ2
NC
A18
NC
RY/BY#
DQ9
DQ1
DQ8
DQ0
A5
A6
A17
A7
OE#
V
SS
CE#
A0
A1
A2
A4
A3
FBGA
Bottom View
21358F-1
P R E L I M I N A R Y
6
Am29LV160B
PIN CONFIGURATION
A0A19
=
20 addresses
DQ0DQ14 =
15 data inputs/outputs
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
=
Selects 8-bit or 16-bit mode
CE#
=
Chip enable
OE#
= Output
enable
WE#
=
Write enable
RESET#
=
Hardware reset pin
RY/BY#
= Ready/Busy
output
(N/A SO 044)
V
CC
=
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
V
SS
=
Device ground
NC
=
Pin not connected internally
LOGIC SYMBOL
21358F-4
20
16 or 8
DQ0DQ15
(A-1)
A0A19
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
(N/A SO 044)
P R E L I M I N A R Y
Am29LV160B
7
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29LV160B
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
C
E
80R
AM29LV160B
T
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F
=
48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S
=
44-Pin Small Outline Package (SO 044)
WC =
48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 8 x 9 mm package
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
Valid Combinations
AM29LV160BT80R,
AM29LV160BB80R
EC, FC, SC, WCC
AM29LV160BT90,
AM29LV160BB90
EC, EI, EE,
FC, FI, FE,
SC, SI, SE,
WCC, WCI, WCE
AM29LV160BT120,
AM29LV160BB120
P R E L I M I N A R Y
8
Am29LV160B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV160B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
0.5 V, X = Don't Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH
), A19:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector
Protection/Unprotection" section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic `1', the device is in
word configuration, DQ15DQ0 are active and control-
led by CE# and OE#.
If the BYTE# pin is set at logic `0', the device is in byte
configuration, and only data I/O pins DQ0DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
. The BYTE# pin determines whether the de-
vice outputs array data in words or bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. The
device remains enabled for read access until the com-
mand register contents are altered.
See "Reading Array Data" for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Operation
CE#
OE# WE# RESET#
Addresses
(Note 1)
DQ0
DQ7
DQ8DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read
L
L
H
H
A
IN
D
OUT
D
OUT
DQ8DQ14 = High-Z,
DQ15 = A-1
Write
L
H
L
H
A
IN
D
IN
D
IN
Standby
V
CC
0.3 V
X
X
V
CC
0.3 V
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
D
IN
X
X
Sector Unprotect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = H, A1 = H,
A0 = L
D
IN
X
X
Temporary Sector
Unprotect
X
X
X
V
ID
A
IN
D
IN
D
IN
High-Z
P R E L I M I N A R Y
Am29LV160B
9
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes
or words. Refer to "Word/Byte Configuration" for
more information.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un-
lock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The "Word/Byte
Program Command Sequence" section has details on
programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A "sector ad-
dress" consists of the address bits required to uniquely
select a sector. The "Command Definitions" section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the "Autoselect Mode" and "Autoselect
Command Sequence" sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to "Write Operation
Status" for more information, and to "AC Characteris-
tics" for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics table, I
CC3
and I
CC4
repre-
sents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
t
A C C
+ 3 0 n s . T h e a u t o m a t i c s l e e p m o d e i s
independent of the CE#, WE#, and OE# control
signals. Standard address access timings provide new
data when addresses are changed. While in sleep
mode, output data is latched and always available to
the system. I
CC4
in the DC Characteristics table
r e p r e s e n ts th e a u to m a t i c sle e p m o d e c u r r e n t
specification.
P R E L I M I N A R Y
10
Am29LV160B
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin to V
IL
for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a "0" (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is "1"), the reset operation is
completed within a time of t
READY
(not during Embed-
ded Algorithms). The system can read data t
RH
after
the RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
P R E L I M I N A R Y
Am29LV160B
11
Table 2.
Sector Address Tables (Am29LV160BT)
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section for more
information.
Sector
A19
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
SA0
0
0
0
0
0
X
X
X
64/32
00000000FFFF
0000007FFF
SA1
0
0
0
0
1
X
X
X
64/32
01000001FFFF
080000FFFF
SA2
0
0
0
1
0
X
X
X
64/32
02000002FFFF
1000017FFF
SA3
0
0
0
1
1
X
X
X
64/32
03000003FFFF
180001FFFF
SA4
0
0
1
0
0
X
X
X
64/32
04000004FFFF
2000027FFF
SA5
0
0
1
0
1
X
X
X
64/32
05000005FFFF
280002FFFF
SA6
0
0
1
1
0
X
X
X
64/32
06000006FFFF
3000037FFF
SA7
0
0
1
1
1
X
X
X
64/32
07000007FFFF
380003FFFF
SA8
0
1
0
0
0
X
X
X
64/32
08000008FFFF
4000047FFF
SA9
0
1
0
0
1
X
X
X
64/32
09000009FFFF
480004FFFF
SA10
0
1
0
1
0
X
X
X
64/32
0A00000AFFFF
5000057FFF
SA11
0
1
0
1
1
X
X
X
64/32
0B00000BFFFF
580005FFFF
SA12
0
1
1
0
0
X
X
X
64/32
0C00000CFFFF
6000067FFF
SA13
0
1
1
0
1
X
X
X
64/32
0D00000DFFFF
680006FFFF
SA14
0
1
1
1
0
X
X
X
64/32
0E00000EFFFF
7000077FFF
SA15
0
1
1
1
1
X
X
X
64/32
0F00000FFFFF
780007FFFF
SA16
1
0
0
0
0
X
X
X
64/32
10000010FFFF
8000087FFF
SA17
1
0
0
0
1
X
X
X
64/32
11000011FFFF
880008FFFF
SA18
1
0
0
1
0
X
X
X
64/32
12000012FFFF
9000097FFF
SA19
1
0
0
1
1
X
X
X
64/32
13000013FFFF
980009FFFF
SA20
1
0
1
0
0
X
X
X
64/32
14000014FFFF
A0000A7FFF
SA21
1
0
1
0
1
X
X
X
64/32
15000015FFFF
A8000AFFFF
SA22
1
0
1
1
0
X
X
X
64/32
16000016FFFF
B0000B7FFF
SA23
1
0
1
1
1
X
X
X
64/32
17000017FFFF
B8000BFFFF
SA24
1
1
0
0
0
X
X
X
64/32
18000018FFFF
C0000C7FFF
SA25
1
1
0
0
1
X
X
X
64/32
19000019FFFF
C8000CFFFF
SA26
1
1
0
1
0
X
X
X
64/32
1A00001AFFFF
D0000D7FFF
SA27
1
1
0
1
1
X
X
X
64/32
1B00001BFFFF
D8000DFFFF
SA28
1
1
1
0
0
X
X
X
64/32
1C00001CFFFF
E0000E7FFF
SA29
1
1
1
0
1
X
X
X
64/32
1D00001DFFFF
E8000EFFFF
SA30
1
1
1
1
0
X
X
X
64/32
1E00001EFFFF
F0000F7FFF
SA31
1
1
1
1
1
0
X
X
32/16
1F00001F7FFF
F8000FBFFF
SA32
1
1
1
1
1
1
0
0
8/4
1F80001F9FFF
FC000FCFFF
SA33
1
1
1
1
1
1
0
1
8/4
1FA0001FBFFF
FD000FDFFF
SA34
1
1
1
1
1
1
1
X
16/8
1FC0001FFFFF
FE000FFFFF
P R E L I M I N A R Y
12
Am29LV160B
Table 3.
Sector Address Tables (Am29LV160BB)
Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See "Word/Byte Configuration" section for more
information.
Sector
A19
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
Byte Mode (x8)
Word Mode (x16)
SA0
0
0
0
0
0
0
0
X
16/8
000000003FFF
0000001FFF
SA1
0
0
0
0
0
0
1
0
8/4
004000005FFF
0200002FFF
SA2
0
0
0
0
0
0
1
1
8/4
006000007FFF
0300003FFF
SA3
0
0
0
0
0
1
X
X
32/16
00800000FFFF
0400007FFF
SA4
0
0
0
0
1
X
X
X
64/32
01000001FFFF
080000FFFF
SA5
0
0
0
1
0
X
X
X
64/32
02000002FFFF
1000017FFF
SA6
0
0
0
1
1
X
X
X
64/32
03000003FFFF
180001FFFF
SA7
0
0
1
0
0
X
X
X
64/32
04000004FFFF
2000027FFF
SA8
0
0
1
0
1
X
X
X
64/32
05000005FFFF
280002FFFF
SA9
0
0
1
1
0
X
X
X
64/32
06000006FFFF
3000037FFF
SA10
0
0
1
1
1
X
X
X
64/32
07000007FFFF
380003FFFF
SA11
0
1
0
0
0
X
X
X
64/32
08000008FFFF
4000047FFF
SA12
0
1
0
0
1
X
X
X
64/32
09000009FFFF
480004FFFF
SA13
0
1
0
1
0
X
X
X
64/32
0A00000AFFFF
5000057FFF
SA14
0
1
0
1
1
X
X
X
64/32
0B00000BFFFF
580005FFFF
SA15
0
1
1
0
0
X
X
X
64/32
0C00000CFFFF
6000067FFF
SA16
0
1
1
0
1
X
X
X
64/32
0D00000DFFFF
680006FFFF
SA17
0
1
1
1
0
X
X
X
64/32
0E00000EFFFF
7000077FFF
SA18
0
1
1
1
1
X
X
X
64/32
0F00000FFFFF
780007FFFF
SA19
1
0
0
0
0
X
X
X
64/32
10000010FFFF
8000087FFF
SA20
1
0
0
0
1
X
X
X
64/32
11000011FFFF
880008FFFF
SA21
1
0
0
1
0
X
X
X
64/32
12000012FFFF
9000097FFF
SA22
1
0
0
1
1
X
X
X
64/32
13000013FFFF
980009FFFF
SA23
1
0
1
0
0
X
X
X
64/32
14000014FFFF
A0000A7FFF
SA24
1
0
1
0
1
X
X
X
64/32
15000015FFFF
A8000AFFFF
SA25
1
0
1
1
0
X
X
X
64/32
16000016FFFF
B0000B7FFF
SA26
1
0
1
1
1
X
X
X
64/32
17000017FFFF
B8000BFFFF
SA27
1
1
0
0
0
X
X
X
64/32
18000018FFFF
C0000C7FFF
SA28
1
1
0
0
1
X
X
X
64/32
19000019FFFF
C8000CFFFF
SA29
1
1
0
1
0
X
X
X
64/32
1A00001AFFFF
D0000D7FFF
SA30
1
1
0
1
1
X
X
X
64/32
1B00001BFFFF
D8000DFFFF
SA31
1
1
1
0
0
X
X
X
64/32
1C00001CFFFF
E0000E7FFF
SA32
1
1
1
0
1
X
X
X
64/32
1D00001DFFFF
E8000EFFFF
SA33
1
1
1
1
0
X
X
X
64/32
1E00001EFFFF
F0000F7FFF
SA34
1
1
1
1
1
X
X
X
64/32
1F00001FFFFF
F8000FFFFF
P R E L I M I N A R Y
Am29LV160B
13
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 2 and 3). Table
4 shows the remaining address bits that are don't care.
When all necessary bits have been set as required, the
programming equipment may then read the corre-
sponding identifier code on DQ7-DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 9. This method
does not require V
ID
. See "Command Definitions" for
details on using the autoselect mode.
Table 4.
Am29LV160B Autoselect Codes (High Voltage Method)
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don't care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD's ExpressFlashTM Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See "Autoselect Mode" for details.
Sector protection/unprotection can be implemented via
two methods.
The primary method requires V
ID
on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.
The alternate method intended only for programming
equipment requires V
ID
on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices. De-
tails on this method are provided in a supplement, pub-
lication number 21468. Contact an AMD representative
to request a copy.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to V
ID
. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once V
ID
is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
Description
Mode
CE#
OE#
WE#
A19
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
Manufacturer ID: AMD
L
L
H
X
X
V
ID
X
L
X
L
L
X
01h
Device ID:
Am29LV160B
(Top Boot Block)
Word
L
L
H
X
X
V
ID
X
L
X
L
H
22h
C4h
Byte
L
L
H
X
C4h
Device ID:
Am29LV160B
(Bottom Boot Block)
Word
L
L
H
X
X
V
ID
X
L
X
L
H
22h
49h
Byte
L
L
H
X
49h
Sector Protection Verification
L
L
H
SA
X
V
ID
X
L
X
H
L
X
01h
(protected)
X
00h
(unprotected)
P R E L I M I N A R Y
14
Am29LV160B
Figure 1.
In-System Sector Protect/Unprotect Algorithms
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Set up sector
address
Wait 150 s
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1
s
First Write
Cycle = 60h?
Data = 01h?
Remove V
ID
from RESET#
Write reset
command
Sector Protect
complete
Yes
Yes
No
PLSCNT
= 25?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Set up first sector
address
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
START
PLSCNT = 1
RESET# = V
ID
Wait 1
s
Data = 00h?
Last sector
verified?
Remove V
ID
from RESET#
Write reset
command
Sector Unprotect
complete
Yes
No
PLSCNT
= 1000?
Yes
Device failed
Increment
PLSCNT
Temporary Sector
Unprotect Mode
No
All sectors
protected?
Yes
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
Set up
next sector
address
No
Yes
No
Yes
No
No
Yes
No
Sector Protect
Algorithm
Sector Unprotect
Algorithm
First Write
Cycle = 60h?
Protect another
sector?
Reset
PLSCNT = 1
21358F-5
P R E L I M I N A R Y
Am29LV160B
15
Figure 2.
Temporary Sector Unprotect Operation
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the
system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte
mode), any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 58. In word mode, the upper address
bits (A7MSB) must be all zeros. To terminate reading
CFI data, the system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 58. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/over-
view/cfi.html. Alternatively, contact an AMD represent-
ative for copies of these documents.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
21358F-6
Table 5.
CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string "QRY"
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
P R E L I M I N A R Y
16
Am29LV160B
Table 6.
System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
1Bh
36h
0027h
V
CC
Min. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Ch
38h
0036h
V
CC
Max. (write/erase)
D7D4: volt, D3D0: 100 millivolt
1Dh
3Ah
0000h
V
PP
Min. voltage (00h = no V
PP
pin present)
1Eh
3Ch
0000h
V
PP
Max. voltage (00h = no V
PP
pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2
N
s
20h
40h
0000h
Typical timeout for Min. size buffer write 2
N
s (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2
N
ms
22h
44h
0000h
Typical timeout for full chip erase 2
N
ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2
N
times typical
24h
48h
0000h
Max. timeout for buffer write 2
N
times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2
N
times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2
N
times typical (00h = not supported)
Table 7.
Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
27h
4Eh
0015h
Device Size = 2
N
byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2
N
(00h = not supported)
2Ch
58h
0004h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0000h
0000h
0040h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
0001h
0000h
0020h
0000h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0080h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
001Eh
0000h
0000h
0001h
Erase Block Region 4 Information
P R E L I M I N A R Y
Am29LV160B
17
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 9 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up
and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Table 8.
Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string "PRI"
43h
86h
0031h
Major version number, ASCII
44h
88h
0030h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock
0 = Required, 1 = Not Required
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
P R E L I M I N A R Y
18
Am29LV160B
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 9 defines the valid register command
sequences. Writing incorrect address and data val-
ues
or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
"AC Characteristics" section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See "Erase Suspend/Erase Resume Commands" for
more information on this mode.
The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the "Reset Com-
mand" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
See "AC Characteristics" for parameters, and to Figure
14 for the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 9 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Tables 2 and 3 for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is
not required to provide further controls or
timings. The device automatically generates the pro-
gram pulses and verifies the programmed cell margin.
Table 9 shows the address and data requirements for
the byte program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See "Write Operation Status"
for information on these status bits.
P R E L I M I N A R Y
Am29LV160B
19
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has reset
to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a "0" back to a "1".
Attempting to do so may halt
the operation and set DQ5 to "1," or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0"
to a "1".
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock by-
pass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The de-
vice then enters the unlock bypass mode. A two-cycle
unlock bypass program command sequence is all that
is required to program in this mode. The first cycle in
this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 9 shows the requirements for the com-
mand sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don't care for both cycles. The device then returns to
reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in "AC
Characteristics" for parameters, and to Figure 17 for
timing diagrams.
Note: See Table 9 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset
during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
21358F-7
P R E L I M I N A R Y
20
Am29LV160B
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
"Write Operation Status" for information on these sta-
tus bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to Figure 18 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock write cycles are then followed by the ad-
dress of the sector to be erased, and the sector erase
command. Table 9 shows the address and data re-
quirements for the sector erase command sequence.
The device does
not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 s, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data.
The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. (Refer to "Write Operation Status" for informa-
tion on these status bits.)
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the "AC Characteristics" section for parameters, and to
Figure 18 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 s time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are "don't-cares" when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 s to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See "Write Operation Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
P R E L I M I N A R Y
Am29LV160B
21
valid operation. See "Autoselect Command Sequence"
for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See Table 9 for erase command sequence.
2. See "DQ3: Sector Erase Timer" for more information.
Figure 4.
Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
21358F-8
P R E L I M I N A R Y
22
Am29LV160B
Table 9.
Am29LV160B Command Definitions
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the
autoselect command sequence, all bus cycles are write
cycles.
4. Data bits DQ15DQ8 are don't cares for unlock and
command cycles.
5. Address bits A19A11 are don't cares for unlock and
command cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array
data.
7. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a
read cycle.
9. The data is 00h for an unprotected sector and 01h for a
protected sector. See "Autoselect Command Sequence" for
more information.
10. Command is valid when device is ready to read array data or
when device is in autoselect mode.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
14. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 25)
First
Second Third Fourth Fifth Sixth
Addr
Data
Addr
Data
Addr
Data Addr
Data
Addr Data
Addr
Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Manufacturer ID
Word
4
555
AA
2AA
55
555
90
X00
01
Byte
AAA
555
AAA
Device ID,
Top Boot Block
Word
4
555
AA
2AA
55
555
90
X01
22C4
Byte
AAA
555
AAA
X02
C4
Device ID,
Bottom Boot Block
Word
4
555
AA
2AA
55
555
90
X01
2249
Byte
AAA
555
AAA
X02
49
Sector Protect Verify
(Note 9)
Word
4
555
AA
2AA
55
555
90
(SA)
X02
XX00
XX01
Byte
AAA
555
AAA
(SA)
X04
00
01
CFI Query (Note 10)
Word
1
55
98
Byte
AA
Program
Word
4
555
AA
2AA
55
555
A0
PA
PD
Byte
AAA
555
AAA
Unlock Bypass
Word
3
555
AA
2AA
55
555
20
Byte
AAA
555
AAA
Unlock Bypass Program (Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
2
XXX
90
XXX
00
Chip Erase
Word
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Byte
AAA
555
AAA
AAA
555
2AA
Sector Erase
Word
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Byte
AAA
555
AAA
AAA
555
Erase Suspend (Note 13)
1
XXX
B0
Erase Resume (Note 14)
1
XXX
30
Cy
c
les
A
u
tos
ele
ct (N
ot
e 8
)
P R E L I M I N A R Y
Am29LV160B
23
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 10 and the following subsections
describe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 s, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to "1";
prior to this, the device outputs the "complement," or
"0." The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 s, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0DQ6 while
Output Enable (OE#) is asserted low. Figure 19, Data#
Polling Timings (During Embedded Algorithms), in the
"AC Characteristics" section illustrates this.
Table 10 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7DQ0
Addr = VA
Read DQ7DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = "1" because
DQ7 may change simultaneously with DQ5.
21358F-9
Figure 5.
Data# Polling Algorithm
P R E L I M I N A R Y
24
Am29LV160B
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to V
CC
. (The RY/BY# pin is not availa-
ble on the 44-pin SO package.)
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 10 shows the outputs for RY/BY#. Figures 13, 14,
17 and 18 shows RY/BY# for read, reset, program, and
erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
approximately 100 s, then returns to reading array
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on "DQ7: Data# Polling").
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 s after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 10 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm in flowchart form,
and the section "Reading Toggle Bits DQ6/DQ2" ex-
plains the algorithm. Figure 20 in the "AC Characteris-
tics" section shows the toggle bit timing diagrams.
Figure 21 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
"DQ2: Toggle Bit II".
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for eras-
ure. (The system may use either OE# or CE# to control
the read cycles.) But DQ2 cannot distinguish whether
the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 10 to compare outputs for
DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section "Reading Toggle Bits DQ6/DQ2"
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20 shows the toggle bit timing dia-
gram. Figure 21 shows the differences between DQ2
and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system
P R E L I M I N A R Y
Am29LV160B
25
must write the reset command to return to reading
array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a "1" to a location that is previously
programmed to "0." Only an erase operation can
change a "0" back to a "1."
Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a "1."
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from "0"
to "1." The system may ignore DQ3 if the system can
guarantee that the time between additional sector
erase commands will always be less than 50
s. See
also the "Sector Erase Command Sequence" section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is "1", the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 10 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7DQ0
Toggle Bit
= Toggle?
Read DQ7DQ0
Twice
Read DQ7DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to "1". See text.
21358F-10
Figure 6.
Toggle Bit Algorithm
(Note 1)
(Notes
1, 2)
P R E L I M I N A R Y
26
Am29LV160B
Table 10.
Write Operation Status
Notes:
1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See "DQ5: Exceeded Timing Limits" for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Operation
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
P R E L I M I N A R Y
Am29LV160B
27
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65
C to +150
C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 65
C to +125
C
Voltage with Respect to Ground
V
CC
(Note 1) . . . . . . . . . . . . . . . . . . 0.5 V to +4.0 V
A9, OE#, and RESET# (Note 2) . . 0.5 V to +12.5 V
All other pins (Note 1). . . . . . . 0.5 V to V
CC
+0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, input or I/O pins may undershoot V
SS
to 2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is
V
CC
+0.5 V.
During voltage transitions, input or I/O pins may overshoot
to V
CC
+2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is -0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
SS
to 2.0 V for periods of up
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 7.
Maximum Negative Overshoot
Waveform
Figure 8.
Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . 0C to +70C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (T
A
) . . . . . . . . 55C to +125C
V
CC
Supply Voltages
V
CC
for regulated voltage range . . . . . . . 3.0 V to 3.6 V
V
CC
for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
21358F-11
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
21358F-1
P R E L I M I N A R Y
28
Am29LV160B
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The I
CC
current listed is typically less than 2 mA/MHz, with OE# at V
IH
. Typical V
CC
is 3.0 V.
2. I
CC
active while Embedded Erase or Embedded Program is in progress.
3. Automatic sleep mode enables the low power mode when addresses remain stable for t
ACC
+ 30 ns. Typical sleep mode
current is 200 nA.
4. Not 100% tested.
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
1.0
A
I
LIT
A9 Input Load Current
V
CC
= V
CC max
; A9 = 12.5 V
35
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC max
1.0
A
I
CC1
V
CC
Active Read Current
(Note 1)
CE# = V
IL,
OE#
=
V
IH,
Byte Mode
5 MHz
9
16
mA
1 MHz
2
4
CE# = V
IL,
OE#
=
V
IH,
Word Mode
5 MHz
9
16
1 MHz
2
4
I
CC2
V
CC
Active Write Current
(Notes 2 and 4)
CE# = V
IL,
OE# = V
IH
20
30
mA
I
CC3
V
CC
Standby Current
V
CC
= V
CC max
;
CE#, RESET# = V
CC
0.3 V
0.2
5
A
I
CC4
V
CC
Standby Current During Reset
V
CC
= V
CC max
;
RESET# = V
SS
0.3 V
0.2
5
A
I
CC5
Automatic Sleep Mode (Note 3)
V
IH
= V
CC
0.3 V;
V
IL
= V
SS
0.3 V
0.2
5
A
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
0.7 x V
CC
V
CC
+ 0.3
V
V
ID
Voltage for Autoselect and
Temporary Sector Unprotect
V
CC
= 3.3 V
11.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 4.0 mA, V
CC
= V
CC min
0.45
V
V
OH1
Output High Voltage
I
OH
= -2.0 mA, V
CC
= V
CC min
0.85 x V
CC
V
V
OH2
I
OH
= -100 A, V
CC
= V
CC min
V
CC
0.4
V
LKO
Low V
CC
Lock-Out Voltage (Note 4)
2.3
2.5
V
P R E L I M I N A R Y
Am29LV160B
29
DC CHARACTERISTICS (Continued)
Zero Power Flash
Note: Addresses are switching at 1 MHz
21358F-13
Figure 9.
I
CC1
Current vs. Time (Showing Active and Automatic Sleep Currents)
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Su
pp
l
y

C
u
rr
ent

i
n
mA
Time in ns
10
8
2
0
1
2
3
4
5
Frequency in MHz
Su
pp
l
y
C
u
rr
e
n
t
i
n

m
A
Note: T = 25
C
21358F-14
Figure 10.
Typical I
CC1
vs. Frequency
2.7 V
3.6 V
4
6
P R E L I M I N A R Y
30
Am29LV160B
TEST CONDITIONS
Table 11.
Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
CL
6.2 k
3.3 V
Device
Under
Test
21358F-15
Figure 11.
Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition
80R
90,
120
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
ns
Input Pulse Levels
0.03.0
V
Input timing measurement
reference levels
1.5 V
Output timing measurement
reference levels
1.5
V
KS000010-PAL
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Output
Measurement Level
Input
21358F-16
Figure 12.
Input Waveforms and Measurement Levels
P R E L I M I N A R Y
Am29LV160B
31
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 11 for test specifications.
Parameter
Description
Speed Option
JEDEC
Std
Test Setup
80R
90
120
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
80
90
120
ns
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
Max
80
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
80
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
25
30
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z (Note 1)
Max
25
30
30
ns
t
OEH
Output Enable
Hold Time (Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
Min
0
ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
OE
0 V
RY/BY#
RESET#
t
DF
t
OH
21358F-17
Figure 13.
Read Operations Timings
P R E L I M I N A R Y
32
Am29LV160B
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested.
Parameter
Description
Speed Option
JEDEC
Std
Test Setup
80R
90
120
Unit
t
READY
RESET# Pin Low (During Embedded Algorithms)
to Read or Write (See Note)
Max
20
s
t
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
RESET# High Time Before Read (See Note)
Min
50
ns
t
RPD
RESET# Low to Standby Mode
Min
20
s
t
RB
RY/BY# Recovery Time
Min
0
ns
RESET#
RY/BY#
RY/BY#
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
t
Ready
CE#, OE#
t
RH
CE#, OE#
Reset Timings during Embedded Algorithms
RESET#
t
RP
t
RB
21358F-18
Figure 14.
RESET# Timings
P R E L I M I N A R Y
Am29LV160B
33
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
80R
90
120
JEDEC
Std
Description
Unit
t
ELFL/
t
ELFH
CE# to BYTE# Switching Low or High
Max
5
ns
t
FLQZ
BYTE# Switching Low to Output HIGH Z
Max
25
30
30
ns
t
FHQV
BYTE# Switching High to Output Active
Min
80
90
120
ns
DQ15
Output
Data Output
(DQ0DQ7)
CE#
OE#
BYTE#
t
ELFL
DQ0DQ14
Data Output
(DQ0DQ14)
DQ15/A-1
Address
Input
t
FLQZ
BYTE#
Switching
from word
to byte
mode
DQ15
Output
Data Output
(DQ0DQ7)
BYTE#
t
ELFH
DQ0DQ14
Data Output
(DQ0DQ14)
DQ15/A-1
Address
Input
t
FHQV
BYTE#
Switching
from byte
to word
mode
21358F-19
Figure 15.
BYTE# Timings for Read Operations
Note: Refer to the Erase/Program Operations table for t
AS
and t
AH
specifications.
21358F-20
Figure 16.
BYTE# Timings for Write Operations
CE#
WE#
BYTE#
The falling edge of the last WE# signal
t
HOLD
(t
AH
)
t
SET
(t
AS
)
P R E L I M I N A R Y
34
Am29LV160B
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Parameter
80R
90
120
JEDEC
Std
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
120
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
WLAX
t
AH
Address Hold Time
Min
45
45
50
ns
t
DVWH
t
DS
Data Setup Time
Min
35
45
50
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
35
35
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Byte
Typ
9
s
Word
Typ
11
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
t
VCS
V
CC
Setup Time (Note 1)
Min
50
s
t
RB
Recovery Time from RY/BY#
Min
0
ns
t
BUSY
Program/Erase Valid to RY/BY# Delay
Min
90
ns
P R E L I M I N A R Y
Am29LV160B
35
AC CHARACTERISTICS
Notes:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
RY/BY#
t
RB
t
BUSY
t
CH
PA
21358F-21
P R E L I M I N A R Y
36
Am29LV160B
AC CHARACTERISTICS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status").
2. Illustration shows device in word mode.
Figure 18.
Chip/Sector Erase Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
RY/BY#
t
RB
t
BUSY
21358F-22
P R E L I M I N A R Y
Am29LV160B
37
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0DQ6
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
21358F-23
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
RY/BY#
t
BUSY
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
t
ACC
t
RC
Valid Data
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Valid Status
VA
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
21358F-24
Figure 20.
Toggle Bit Timings (During Embedded Algorithms)
P R E L I M I N A R Y
38
Am29LV160B
AC CHARACTERISTICS
Temporary Sector Unprotect
Note: Not 100% tested.
Parameter
80R
90
120
JEDEC
Std.
Description
Unit
t
VIDR
V
ID
Rise and Fall Time (See Note)
Min
500
ns
t
RSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
s
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
21358F-25
Figure 21.
DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
t
VIDR
12 V
0 or 3 V
CE#
WE#
RY/BY#
t
VIDR
t
RSP
Program or Erase Command Sequence
21358F-26
Figure 22.
Temporary Sector Unprotect Timing Diagram
P R E L I M I N A R Y
Am29LV160B
39
AC CHARACTERISTICS
Sector Protect: 100 s
Sector Unprotect: 10 ms
1 s
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h
60h
40h
Valid*
Valid*
Valid*
Status
Sector Protect/Unprotect
Verify
V
ID
V
IH
Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
21358F-27
Figure 23.
Sector Protect/Unprotect Timing Diagram
P R E L I M I N A R Y
40
Am29LV160B
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Parameter
80R
90
120
JEDEC
Std
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
80
90
120
ns
t
AVEL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
45
50
ns
t
DVEH
t
DS
Data Setup Time
Min
35
45
50
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
35
35
50
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
30
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Byte
Typ
9
s
Word
Typ
11
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
P R E L I M I N A R Y
Am29LV160B
41
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
RY/BY#
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D
OUT
= data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
21358F-28
Figure 24.
Alternate CE# Controlled Write Operation Timings
P R E L I M I N A R Y
42
Am29LV160B
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
C, 3.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, V
CC
= 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 9 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Includes all pins except V
CC
. Test conditions: V
CC
= 3.0 V, one pin at a time.
TSOP AND SO PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
15
s
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
25
s
Byte Programming Time
9
300
s
Excludes system level
overhead (Note 5)
Word Programming Time
11
360
s
Chip Programming Time
(Note 3)
Byte Mode
18
54
s
Word Mode
12
36
s
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
1.0 V
V
CC
+ 1.0 V
V
CC
Current
100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
7.5
9
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
C
10
Years
125
C
20
Years
P R E L I M I N A R Y
Am29LV160B
43
PHYSICAL DIMENSIONS*
TS 048--48-Pin Standard TSOP (measured in millimeters)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
TSR048--48-Pin Reverse TSOP (measured in millimeters)
* For reference only. BSC is an ANSI standard for Basic Space Centering.
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48-2
TS 048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC
0
5
0.08
0.20
48
25
1
24
18.30
18.50
19.80
20.20
11.90
12.10
SEATING PLANE
0.05
0.15
0.50 BSC
0.95
1.05
16-038-TS48
TSR048
DT95
8-8-96 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0.25MM (0.0098") BSC
0
5
0.08
0.20
P R E L I M I N A R Y
44
Am29LV160B
PHYSICAL DIMENSIONS
FGC--48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm (measured in millimeters)
7.80
8.20
8.80
9.20
DATUM B
DATUM A
INDEX
0.025
CHAMFER
0.15 M Z B M
0.15 M Z B M
5.60
BSC
0.40
4.00
BSC
0.08 M Z A B
0.10 Z
0.25
0.45
0.80
DETAIL A
0.20 Z
DETAIL A
1.20 MAX
0.40
0.08 (48x)
0.40
16-038-FGC-2
EG137
12-2-97 lv
P R E L I M I N A R Y
Am29LV160B
45
PHYSICAL DIMENSIONS
SO 044--44-Pin Small Outline Package (measured in millimeters)
44
23
1
22
13.10
13.50
15.70
16.30
1.27 NOM.
28.00
28.40
2.17
2.45
0.35
0.50
0.10
0.35
2.80
MAX.
SEATING
PLANE
16-038-SO44-2
SO 044
DF83
8-8-96 lv
0.10
0.21
0.60
1.00
0
8
END VIEW
SIDE VIEW
TOP VIEW
P R E L I M I N A R Y
46
Am29LV160B
REVISION SUMMARY FOR AM29LV160B
Revision F
Distinctive Characteristics
Changed typical read and program/erase current spec-
ifications.
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Figure 1, In-System Sector Protect/Unprotect
Algorithm
Corrected A6 to 0, Changed wait specification to 150
s on sector protect and 15 ms on sector unprotect.
DC Characteristics
Changed typical read and program/erase current spec-
ifications.
AC Characteristics
Alternate CE# Controlled Erase/Program Operations:
Changed t
CP
to 35 ns for 70R, 80, and 90 speed
options.
Erase and Programming Performance
Device now has a guaranteed minimum endurance of
1,000,000 write cycles.
Physical Dimensions
Corrected dimensions for package length and width in
FBGA illustration (standalone data sheet version).
Revision F+1
Table 9, Command Definitions
Corrected the byte-mode address in the sixth write
cycle of the chip erase command sequence to AAAh.
Revision F+2
Figure 1, In-System Sector Protect/Unprotect
Algorithms
In the sector protect algorithm, added a "Reset
PLSCNT=1" box in the path from "Protect another sec-
tor?" back to setting up the next sector address.
DC Characteristics
Changed I
CC1
test conditions and Note 1 to indicate
that OE# is at V
IH
for the listed current.
AC Characteristics
Erase/Program Operations; Alternate CE# Controlled
Erase/Program Operations: Corrected the notes refer-
ence for t
WHWH1
and t
WHWH2
. These parameters are
100% tested. Corrected the note reference for t
VCS
.
This parameter is not 100% tested.
Temporary Sector Unprotect Table
Added note reference for t
VIDR
. This parameter is not
100% tested.
Figure 23, Sector Protect/Unprotect Timing
Diagram
A valid address is not required for the first write cycle;
only the data 60h.
Erase and Programming Performance
In Note 2, the worst case endurance is now 1 million cy-
cles.
Trademarks
Copyright 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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