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Datasheet: 29F800 (Advanced Micro Devices)

8 Megabit (1 M X 8-bit/512 K X 16-bit) Cmos 5.0 Volt-only, Boot Sector Flash Memory

 

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Advanced Micro Devices

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PRELIMINARY
Publication# 21504
Rev: C Amendment/+1
Issue Date: April 1998
Am29F800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 5.0 Volt-only, Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
-- 5.0 Volt-only operation for read, erase, and
program operations
-- Minimizes system level requirements
s
Manufactured on 0.35 m process technology
-- Compatible with 0.5 m Am29F800 device
s
High performance
-- Access times as fast as 55 ns
s
Low power consumption (typical values at 5
MHz)
-- 1 A standby mode current
-- 20 mA read current (byte mode)
-- 28 mA read current (word mode)
-- 30 mA program/erase current
s
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
-- One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
-- Supports full chip erase
-- Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 1,000,000 program/erase cycles per
sector guaranteed
s
Package option
-- 48-pin TSOP
-- 44-pin SO
s
Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power-supply Flash
-- Superior inadvertent write protection
s
Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
s
Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting
program or erase cycle completion
s
Erase Suspend/Erase Resume
-- Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data
2
Am29F800B
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F800B is an 8 Mbit, 5.0 volt-only Flash
memory organized as 1,048,576 bytes or 524,288
words. The device is offered in 44-pin SO and 48-pin
TSOP packages. The word-wide data (x16) appears on
DQ15DQ0; the byte-wide (x8) data appears on DQ7
DQ0. This device is designed to be programmed in-
system with the standard system 5.0 volt V
CC
supply.
A 12.0 V V
PP
is not required for write or erase opera-
tions. The device can also be programmed in standard
EPROM programmers.
This device is manufactured using AMD's 0.35 m
process technology, and offers all the features and ben-
efits of the Am29F800, which was manufactured using
0.5 m process technology.
The standard device offers access times of 55, 70, 90,
120, and 150 ns, allowing high speed microprocessors
to operate without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program
algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The system can place the device into the standby
mode
. Power consumption is greatly reduced in
this mode.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y a n d c o s t
effectiveness. The device electrically erases all
b i t s w i t h i n a s e c t o r s i m u l t a n e o u s l y v i a
F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s
programmed using hot electron injection.
Am29F800B
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
Family Part Number
Am29F800B
Speed Option
V
CC
= 5.0 V 5%
-55
V
CC
= 5.0 V 10%
-70
-90
-120
-150
Max access time, ns (t
ACC
)
55
70
90
120
150
Max CE# access time, ns (t
CE
)
55
70
90
120
150
Max OE# access time, ns (t
OE
)
30
30
35
50
55
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
A
d
d
res
s L
atch
A0A18
21504C-1
4
Am29F800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
21504C-2
48-Pin TSOP--Standard Pinout
48-Pin TSOP--Reverse Pinout
Am29F800B
5
P R E L I M I N A R Y
CONNECTION DIAGRAMS
PIN CONFIGURATION
A0A18
=
19 addresses
DQ0DQ14 =
15 data inputs/outputs
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
=
Selects 8-bit or 16-bit mode
CE#
=
Chip enable
OE#
= Output
enable
WE#
=
Write enable
RESET#
=
Hardware reset pin, active low
RY/BY#
= Ready/Busy#
output
V
CC
=
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
=
Device ground
NC
=
Pin not connected internally
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
SO
21504C-3
21504C-4
19
16 or 8
DQ0DQ15
(A-1)
A0A18
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
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