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Datasheet: 29F040 (Advanced Micro Devices)

4 Megabit (512 K X 8-bit) Cmos 5.0 Volt-only, Uniform Sector Flash Memory

 

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Advanced Micro Devices

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PRELIMINARY
Publication# 21445
Rev: B Amendment/+2
Issue Date: April 1998
Am29F040B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Distinctive Characteristics
s
5.0 V
10% for read and write operations
-- Minimizes system level power requirements
s
Manufactured on 0.35
m process technology
-- Compatible with 0.5 m Am29F040 device
s
High performance
-- Access times as fast as 55 ns
s
Low power consumption
-- 20 mA typical active read current
-- 30 mA typical program/erase current
-- 1 A typical standby current (standard access
time to active mode)
s
Flexible sector architecture
-- 8 uniform sectors of 64 Kbytes each
-- Any combination of sectors can be erased
-- Supports full chip erase
-- Sector protection:
A hardware method of locking sectors to prevent
any program or erase operations within that
sector
s
Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
s
Minimum 1,000,000 program/erase cycles per
sector guaranteed
s
Package options
-- 32-pin PLCC, TSOP, or PDIP
s
Compatible with JEDEC standards
-- Pinout and software compatible with
single-power-supply Flash standard
-- Superior inadvertent write protection
s
Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase cycle completion
s
Erase Suspend/Erase Resume
-- Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
2
Am29F040B
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F040B is a 4 Mbit, 5.0 volt-only Flash mem-
ory organized as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are divided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0DQ7. The Am29F040B is offered
in 32-pin PLCC, TSOP, and PDIP packages. This de-
vice is designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. A 12.0 volt V
PP
is
not required for write or erase operations. The device
can also be programmed in standard EPROM pro-
grammers.
This device is manufactured using AMD's 0.35 m
process technology, and offers all the features and ben-
efits of the Am29F040, which was manufactured using
0 . 5 m p r o c e s s t e c h n o l o g y. I n a d d t i o n , t h e
Am29F040B has a second toggle bit, DQ2, and also
offers the ability to program in the Erase Suspend
mode.
The standard Am29F040B offers access times of 55,
70, 90, 120, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using stan-
dard microprocessor write timings. Register contents
serve as input to an internal state-machine that con-
trols the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program
algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The system can place the device into the standby
mode
. Power consumption is greatly reduced in
this mode.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnel-
ing. The data is programmed using hot electron injec-
tion.
Am29F040B
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Note: See the "AC Characteristics" section for more information.
BLOCK DIAGRAM
Family Part Number
Am29F040B
Speed Option
V
CC
= 5.0 V
5%
-55
V
CC
= 5.0 V
10%
-70
-90
-120
-150
Max access time, ns (t
ACC
)
55
70
90
120
150
Max CE# access time, ns (t
CE
)
55
70
90
120
150
Max OE# access time, ns (t
OE
)
25
30
35
50
55
Erase Voltage
Generator
Y-Gating
Cell Matrix
X-Decoder
Y-Decoder
Ad
dre
ss L
atc
h
Chip Enable
Output Enable
Logic
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
WE#
CE#
OE#
A0A18
STB
STB
DQ0DQ7
V
CC
V
SS
21445B-1
Data Latch
Input/Output
Buffers
4
Am29F040B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
21445B-2
V
CC
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PDIP
5
6
7
8
9
10
11
12
13
17 18 19 20
16
15
14
29
28
27
26
25
24
23
22
21
1
31 30
2
3
4
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
A18
V
CC
WE#
A17
21445B-3
PLCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
21445B-4
32-Pin Standard TSOP
32-Pin Reverse TSOP
Am29F040B
5
P R E L I M I N A R Y
PIN CONFIGURATION
A0A18
=
Address Inputs
DQ0DQ7 =
Data Input/Output
CE#
=
Chip Enable
WE#
=
Write Enable
OE#
=
Output Enable
V
SS
=
Device Ground
V
CC
=
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
LOGIC SYMBOL
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
19
8
DQ0DQ7
A0A18
CE#
OE#
WE#
21445B-5
DEVICE NUMBER/DESCRIPTION
Am29F040B
4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Sector Erase Flash Memory
5.0 V Read, Program, and Erase
Am29F040B
-55
E
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C
=
Commercial (0
C to +70
C)
I
=
Industrial (40
C to +85
C)
E
=
Extended (55
C to +125
C)
PACKAGE TYPE
P =
32-Pin Plastic DIP (PD 032)
J
=
32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E =
32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F =
32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
Valid Combinations
Am29F040B-55
JC, JI, JE, EC, EI, EE, FC, FI, FE
Am29F040B-70
Am29F040B-90
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
Am29F040B-120
Am29F040B-150
6
Am29F040B
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29F040B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
0.5 V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note: See the section on Sector Protection for more information.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See "Reading Array Data" for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
"sector address" consists of the address bits required
to uniquely select a sector. See the "Command Defini-
tions" section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the "Autoselect Mode" and "Autoselect
Command Sequence" sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to "Write Operation
Status" for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
Operation
CE#
OE#
WE#
A0A20
DQ0DQ7
Read
L
L
H
A
IN
D
OUT
Write
L
H
L
A
IN
D
IN
CMOS Standby
V
CC
0.5 V
X
X
X
High-Z
TTL Standby
H
X
X
X
High-Z
Output Disable
L
H
H
X
High-Z
Am29F040B
7
P R E L I M I N A R Y
The device enters the CMOS standby mode when the
CE# pin is held at V
CC
0.5 V. (Note that this is a more
restricted voltage range than V
IH
.) The device enters
the TTL standby mode when CE# is held at V
IH
. The
device requires the standard access time (t
CE
) before it
is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics tables represents the
standby current specification.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2.
Sector Addresses Table
Note: All sectors are 64 Kbytes in size.
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don't care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require V
ID
. See
"Command Definitions" for details on using the autose-
lect mode.
Sector A18
A17
A16
Address
Range
SA0
0
0
0
00000h0FFFFh
SA1
0
0
1
10000h1FFFFh
SA2
0
1
0
20000h2FFFFh
SA3
0
1
1
30000h3FFFFh
SA4
1
0
0
40000h4FFFFh
SA5
1
0
1
50000h5FFFFh
SA6
1
1
0
60000h6FFFFh
SA7
1
1
1
70000h7FFFFh
8
Am29F040B
P R E L I M I N A R Y
Table 3.
Am29F040B Autoselect Codes (High Voltage Method)
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in a
supplement, publication number 19957. Contact an
AMD representative to obtain a copy of the appropriate
document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD's ExpressFlashTM Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See "Autoselect Mode" for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values
or writing them in the im-
proper sequence
resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
"AC Characteristics" section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
Description
A18A16
A15A10
A9
A8A7
A6
A5A2
A1
A0
Identifier Code on
DQ7-DQ0
Manufacturer ID: AMD
X
X
V
ID
X
V
IL
X
V
IL
V
IL
01h
Device ID: Am29F040B
X
X
V
ID
X
V
IL
X
V
IL
V
IH
A4h
Sector Protection
Verification
Sector
Address
X
V
ID
X
V
IL
X
V
IH
V
IL
01h (protected)
00h (unprotected)
Am29F040B
9
P R E L I M I N A R Y
data with the same exception. See "Erase Suspend/
Erase Resume Commands" for more information on
this mode.
The system
must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the "Reset Com-
mand" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7
or DQ6. See "Write Operation Status" for information
on these status bits.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a "0" back to a "1".
Attempting to do so may halt
the operation and set DQ5 to "1", or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0"
to a "1".
10
Am29F040B
P R E L I M I N A R Y
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 1.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See "Write
Operation Status" for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 s, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data.
The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
Refer to "Write Operation Status" for information on
these status bits.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
21445B-6
Am29F040B
11
P R E L I M I N A R Y
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the "AC Characteristics" section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 s time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are "don't-cares" when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 s to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See "Write Operation Status" for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See "Autoselect Command Sequence"
for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See "DQ3: Sector Erase Timer" for more information.
Figure 2.
Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
21445B-7
12
Am29F040B
P R E L I M I N A R Y
Table 4.
Am29F040B Command Definitions
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A18A16 select a unique sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A18A11 are don't cares for unlock and
command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See "Autoselect Command Sequence" for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 24)
First
Second Third Fourth Fifth Sixth
Addr
Data
Addr
Data
Addr
Data Addr
Data
Addr Data
Addr
Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Autoselect
(Note 7)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID
4
555
AA
2AA
55
555
90
X01
A4
Sector Protect Verify
(Note 8)
4
555
AA
2AA
55
555
90
SA
X02
XX00
XX01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 9)
1
XXX
B0
Erase Resume (Note 10)
1
XXX
30
Cy
c
l
es
Am29F040B
13
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 5 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
sys tem w he th er a n E m be dd e d Alg or ith m is i n
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2 s, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to "1";
prior to this, the device outputs the "complement," or
"0." The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 s, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7DQ0 on the following read cycles. This is be-
c a u s e D Q 7 m ay c h a n g e a s y n c h r o n o u s ly w it h
DQ0DQ6 while Output Enable (OE#) is asserted low.
The Data# Polling Timings (During Embedded Algo-
rithms) figure in the "AC Characteristics" section illus-
trates this.
Table 5 shows the outputs for Data# Polling on DQ7.
Figure 3 shows the Data# Polling algorithm.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7DQ0
Addr = VA
Read DQ7DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = "1" because
DQ7 may change simultaneously with DQ5.
21445B-8
Figure 3.
Data# Polling Algorithm
14
Am29F040B
P R E L I M I N A R Y
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 s, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on "DQ7: Data# Polling").
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 s after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
"AC Characteristics" section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on "DQ2: Toggle Bit II".
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 5 to compare outputs
for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section "DQ2: Toggle Bit II" explains the
algorithm. See also the "DQ6: Toggle Bit I" subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7DQ0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Am29F040B
15
P R E L I M I N A R Y
The DQ5 failure condition may appear if the system
tries to program a "1" to a location that is previously pro-
grammed to "0." Only an erase operation can change
a "0" back to a "1."
Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from "0" to "1." The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50 s. See also the "Sector Erase Command Se-
quence" section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is "1", the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 5 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7DQ0
Toggle Bit
= Toggle?
Read DQ7DQ0
Twice
Read DQ7DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to "1". See text.
21445B-9
Figure 4.
Toggle Bit Algorithm
(Notes
1, 2)
Note 1
16
Am29F040B
P R E L I M I N A R Y
Table 5.
Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See "DQ5: Exceeded Timing Limits" for more information.
Operation
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
Am29F040B
17
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65C to +125C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55C to +125C
Voltage with Respect to Ground
V
CC
(Note 1) . . . . . . . . . . . . . . . . . 2.0 V to 7.0 V
A9, OE# (Note 2) . . . . . . . . . . . . . 2.0 V to 12.5 V
All other pins (Note 1) . . . . . . . . . . 2.0 V to 7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, inputs may undershoot V
SS
to 2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is V
CC
+ 0.5 V. During
voltage transitions, input and I/O pins may overshoot to
V
CC
+ 2.0 V for periods up to 20 ns. See Figure 6.
2. Minimum DC input voltage on A9 pin is 0.5 V. During
voltage transitions, A9 and OE# may undershoot V
SS
to
2.0 V for periods of up to 20 ns. See Figure 5. Maximum
DC input voltage on A9 and OE# is 12.5 V which may
overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
Figure 5.
Maximum Negative Overshoot
Waveform
Figure 6.
Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commer cial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . 0
C to +70
C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (T
A
) . . . . . . . . 55C to +125C
V
CC
Supply Voltages
V
CC
for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
V
CC
for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
21445B-10
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
21445B-11
18
Am29F040B
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
CMOS Compatible
Notes for DC Characteristics (both tables):
1. The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. Not 100% tested.
4. For CMOS mode only, I
CC3
= 20 A max at extended temperatures (> +85C).
Parameter
Symbol
Parameter Description
Test Description
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
A
I
LIT
A9 Input Load Current
V
CC
= V
CC
Max, A9 = 12.5 V
50
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
A
I
CC1
V
CC
Active Read Current (Note 1)
CE# = V
IL,
OE# = V
IH
20
30
mA
I
CC2
V
CC
Active Write (Program/Erase)
Current (Notes 2, 3)
CE#
= V
IL,
OE# =
V
IH
30
40
mA
I
CC3
V
CC
Standby Current
V
CC
= V
CC
Max, CE# = V
IH
0.4
1.0
mA
V
IL
Input Low Level
0.5
0.8
V
V
IH
Input High Level
2.0
V
CC
+ 0.5
V
V
ID
Voltage for Autoselect
and Sector Protect
V
CC
= 5.25 V
10.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 12 mA, V
CC
= V
CC
Min
0.45
V
V
OH
Output High Level
I
OH
= 2.5 mA, V
CC
= V
CC
Min
2.4
V
V
LKO
Low V
CC
Lock-Out Voltage
3.2
4.2
V
Parameter
Symbol
Parameter Description
Test Description
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
A
I
LIT
A9 Input Load Current
V
CC
= V
CC
Max, A9 = 12.5 V
50
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
, V
CC
= V
CC
Max
1.0
A
I
CC1
V
CC
Active Read Current
(Note 1)
CE# = V
IL,
OE# = V
IH
20
30
mA
I
CC2
V
CC
Active Program/Erase Current
(Notes 2, 3)
CE#
= VIL,
OE#
= VIH
30
40
mA
I
CC3
V
CC
Standby Current (Note 4)
V
CC
= V
CC
Max, CE# = V
CC
0.5 V
1
5
A
V
IL
Input Low Level
0.5
0.8
V
V
IH
Input High Level
0.7 x V
CC
V
CC
+ 0.3
V
V
ID
Voltage for Autoselect and Sector
Protect
V
CC
= 5.25 V
10.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 12.0 mA, V
CC
= V
CC
Min
0.45
V
V
OH1
Output High Voltage
I
OH
= 2.5 mA, V
CC
= V
CC
Min
0.85 V
CC
V
V
OH2
I
OH
= 100
A, V
CC
= V
CC
Min
V
CC
0.4
V
V
LKO
Low V
CC
Lock-out Voltage
3.2
4.2
V
Am29F040B
19
P R E L I M I N A R Y
TEST CONDITIONS
Table 6.
Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
CL
6.2 k
5.0 V
Device
Under
Test
21445B-12
Figure 7.
Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition
-55
All others Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
100 pF
Input Rise and Fall Times
5
20
ns
Input Pulse Levels
0.03.0
0.452.4
V
Input timing measurement
reference levels
1.5 0.8
V
Output timing measurement
reference levels
1.5
2.0
V
KS000010-PAL
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
20
Am29F040B
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Only Operations
Notes:
1. See Figure 7 and Table 6 for test conditions.
2. Output driver disable time.
3. Not 100% tested.
Parameter Symbols
Description
Test Setup
Speed Options (Note 1)
Unit
JEDEC
Standard
-55
-70
-90
-120
-150
t
AVAV
t
RC
Read Cycle Time (Note 3)
Min
55
70
90
120
150
ns
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL,
OE# = V
IL
Max
55
70
90
120
150
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
55
70
90
120
150
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
30
35
50
55
ns
t
OEH
Output Enable Hold
Time (Note 3)
Read
Min
0
0
0
0
0
ns
Toggle and
Data# Polling
Min
10
10
10
10
10
ns
t
EHQZ
t
DF
Chip Enable to Output High Z
(Notes 2, 3)
Max
18
20
20
30
35
ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Notes 2, 3)
18
20
20
30
35
ns
t
AXQX
t
OH
Output Hold Time from Addresses, CE#
or OE#, Whichever Occurs First
Min
0
0
0
0
0
ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
OE
0 V
t
DF
t
OH
21445B-13
Figure 8.
Read Operation Timings
Am29F040B
21
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
Parameter Symbols
Description
Speed Options
Unit
JEDEC
Std.
-55
-70
-90
-120
-150
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
55
70
90
120
150
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
WLAX
t
AH
Address Hold Time
Min
40
45
45
50
50
ns
t
DVWH
t
DS
Data Setup Time
Min
25
30
45
50
50
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHWL
t
GHWL
Read Recover Time Before Write
(OE# high to WE# low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
45
50
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
20
ns
t
WHWH1
t
WHWH1
Byte Programming Operation
(Note 2)
Typ
7
s
t
WHWH2
t
WHWH2
Sector Erase Operation
(Note 2)
Typ
1
sec
t
VCS
V
CC
Set Up Time (Note 1)
Min
50
s
22
Am29F040B
P R E L I M I N A R Y
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
t
CH
PA
Note: PA = program address, PD = program data, D
OUT
is the true data at the program address.
21445B-14
Figure 9.
Program Operation Timings
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
Note:
SA = Sector Address. VA = Valid Address for reading status data.
21445B-15
Figure 10.
Chip/Sector Erase Operation Timings
Am29F040B
23
P R E L I M I N A R Y
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0DQ6
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle .
21445B-16
Figure 11.
Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
t
ACC
t
RC
Valid Data
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Valid Status
VA
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21445B-17
Figure 12.
Toggle Bit Timings (During Embedded Algorithms)
24
Am29F040B
P R E L I M I N A R Y
AC CHARACTERISTICS
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes
Notes:
1. Not 100% tested.
2. See the "Erase And Programming Performance" section for more information.
Note: Both DQ6 and DQ2 toggle with OE# or CE#. See the text on DQ6 and DQ2 in the "Write Operation Status" section for more
information.
21445B-18
Figure 13.
DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
DQ2 and DQ6 toggle with OE# and CE#
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
Parameter Symbols
Description
Speed Options
Unit
JEDEC
Standard
-55
-70
-90
-120
-150
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
55
70
90
120
150
ns
t
AVEL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
40
45
45
50
50
ns
t
DVEH
t
DS
Data Setup Time
Min
25
30
45
50
50
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
GHEL
t
GHEL
Read Recover Time Before Write
Min
0
ns
t
WLEL
t
WS
CE# Setup Time
Min
0
ns
t
EHWH
t
WH
CE# Hold Time
Min
0
ns
t
ELEH
t
CP
Write Pulse Width
Min
30
35
45
50
50
ns
t
EHEL
t
CPH
Write Pulse Width High
Min
20
20
20
20
20
ns
t
WHWH1
t
WHWH1
Byte Programming Operation
(Note 2)
Typ
7
s
t
WHWH2
t
WHWH2
Sector Erase Operation
(Note 2)
Typ
1
sec
Am29F040B
25
P R E L I M I N A R Y
AC CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
C, 5.0 V V
CC
, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, V
CC
= 4.5 V (4.75 V for -55), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
8
sec
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
8
64
sec
Byte Programming Time
7
300
s
Excludes system-level overhead
(Note 5)
Chip Programming Time (Note 3)
3.6
10.8
sec
t
GHEL
t
WS
OE#
CE#
WE#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
t
BUSY
Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D
OUT
= Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
21445B-19
Figure 14.
Alternate CE# Controlled Write Operation Timings
26
Am29F040B
P R E L I M I N A R Y
LATCHUP CHARACTERISTICS
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
PLCC AND PDIP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
DATA RETENTION
Min
Max
Input Voltage with respect to V
SS
on all I/O pins
1.0 V
V
CC
+ 1.0 V
V
CC
Current
100 mA
+100 mA
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
7.5
9
pF
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
4
6
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
Control Pin Capacitance
V
PP
= 0
8
12
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
C
10
Years
125
C
20
Years
Am29F040B
27
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.670
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160
.016
.022
SEATING PLANE
.015
.060
16-038-S_AG
PD 032
EC75
5-28-97 lv
32
17
16
.630
.700
0
10
.600
.625
.009
.015
.050 REF.
.026
.032
TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF.
.490
.530
28
Am29F040B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TS 032
32-Pin Standard Thin Small Package (measured in millimeters)
Pin 1 I.D.
1
18.30
18.50
7.90
8.10
0.50 BSC
0.05
0.15
0.95
1.05
16-038-TSOP-2
TS 032
DA95
3-25-97 lv
19.80
20.20
1.20
MAX
0.50
0.70
0.10
0.21
0
5
0.08
0.20
Am29F040B
29
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TSR032
32-Pin Reversed Thin Small Outline Package (measured in millimeters)
1
18.30
18.50
19.80
20.20
7.90
8.10
0.50 BSC
0.05
0.15
0.95
1.05
16-038-TSOP-2
TSR032
DA95
3-25-97 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0
5
0.08
0.20
30
Am29F040B
P R E L I M I N A R Y
REVISION SUMMARY FOR AM29F040B
Global
Formatted for consistency with other 5.0 volt-only data
data sheets.
Revision B+1
AC Characteristics, Erase and Program Operations
Added Note references to t
WHWH1
. Corrected the pa-
rameter symbol for V
CC
Set-up Time to t
VCS
; the spec-
ification is 50
s minimum. Deleted the last row in table.
Revision B+2
Distinctive Characteristics
Changed minimum 100K write/erase cycles guaran-
teed to 1,000,000.
Ordering Infomation
Added extended temperature availability to the -55 and
-70 speed options.
AC Characteristics
Erase/Program Operations; Erase and Program Oper-
ations Alternate CE# Controlled Writes: Corrected the
notes reference for t
WHWH1
and t
WHWH2
. These param-
eters are 100% tested. Corrected the note reference for
t
VCS
. This parameter is not 100% tested.
Erase and Programming Performance
Changed minimum 100K program and erase cycles
guaranteed to 1,000,000.
Trademarks
Copyright 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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