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Datasheet: 29F002 (Advanced Micro Devices)

2 Megabit (256 K X 8-bit) Cmos 5.0 Volt-only Boot Sector Flash Memory

 

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Advanced Micro Devices

Document Outline

PRELIMINARY
Publication# 20818
Rev: C Amendment/+2
Issue Date: March 1998
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
-- 5.0 Volt-only operation for read, erase, and
program operations
-- Minimizes system level requirements
s
High performance
-- Access times as fast as 55 ns
s
Low power consumption (typical values at 5
MHz)
-- 1 A standby mode current
-- 20 mA read current
-- 30 mA program/erase current
s
Flexible sector architecture
-- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
-- Supports full chip erase
-- Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked via programming
equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
-- Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
-- Embedded Program algorithm automatically
writes and verifies data at specified addresses
s
Minimum 100,000 write cycle guarantee per
sector
s
Package option
-- 32-pin PDIP
-- 32-pin TSOP
-- 32-pin PLCC
s
Compatibility with JEDEC standards
-- Pinout and software compatible with single-
power supply Flash
-- Superior inadvertent write protection
s
Data# Polling and toggle bits
-- Provides a software method of detecting
program or erase operation completion
s
Erase Suspend/Erase Resume
-- Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
s
Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading
array data (not available on Am29F002N)
2
Am29F002/Am29F002N
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only
Flash memory devices organized as 262,144 bytes.
The Am29F002 offers the RESET# function, the
Am29F002N does not. The data appears on DQ7
DQ0. The device is offered in 32-pin PLCC, 32-pin
TSOP, and 32-pin PDIP packages. This device is
designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. No V
PP
is
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 5.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program
algorithm--an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm--an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
(This feature is not available on the Am29F002N.)
The system can place the device into the standby
mode
. Power consumption is greatly reduced in this
mode.
AMD's Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Am29F002/Am29F002N
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Note: See "AC Characteristics" for full specifications.
BLOCK DIAGRAM
Family Part Number
Am29F002/Am29F002N
Speed Option
V
CC
= 5.0 V 5%
-55
V
CC
= 5.0 V 10%
-70
-90
-120
Max access time, ns (t
ACC
)
55
70
90
120
Max CE# access time, ns (t
CE
)
55
70
90
120
Max OE# access time, ns (t
OE
)
30
30
35
50
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
V
CC
Detector
State
Control
Command
Register
V
CC
V
SS
WE#
CE#
OE#
STB
STB
DQ0
DQ7
Sector Switches
RESET#
Data
Latch
Y-Gating
Cell Matrix
Ad
dre
ss L
atc
h
A0A17
20818C-1
n/a Am29F00N
4
Am29F002/Am29F002N
P R E L I M I N A R Y
CONNECTION DIAGRAMS
3
4
5
2
1
9
10
11
12
13
27
26
25
24
23
7
8
22
21
6
32
31
20
14
30
29
28
15
16
19
18
17
A6
A5
A4
A3
A2
A1
A0
A16
DQ0
A15
A12
A7
DQ1
DQ2
VSS
A8
A9
A11
OE#
A10
CE#
DQ7
VCC
WE#
DQ6
A17
A14
A13
DQ5
DQ4
DQ3
NC
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A9
A8
A13
A14
A17
WE#
V
CC
RESET#
A16
A15
A12
A7
A6
A5
A4
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17 18 19 20
16
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A12
A15
A16
RESET#
V
CC
WE#
A17
DQ1
DQ2
V
SS
DQ3
DQ4
DQ5
DQ6
20818C-2
PDIP
Standard TSOP
PLCC
NC on Am29F00N
NC on Am29F00N
NC on Am29F00N
RESET#
Am29F002/Am29F002N
5
P R E L I M I N A R Y
PIN CONFIGURATION
A0A17
=
18 addresses
DQ0DQ7 =
8 data inputs/outputs
CE#
=
Chip enable
OE#
= Output
enable
WE#
=
Write enable
RESET#
=
Hardware reset pin, active low
(not available on Am29F002N)
V
CC
=
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
V
SS
=
Device ground
NC
=
Pin not connected internally
LOGIC SYMBOL
20818C-3
18
8
DQ0DQ7
A0A17
CE#
OE#
WE#
RESET#
N/C on Am29F002N
6
Am29F002/Am29F002N
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Product
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am29F002/Am29F002N
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
Am29F002
-70
P
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0
C to +70
C)
I = Industrial (-40
C to +85
C)
E = Extended (55
C to +125
C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package
(TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
B
T
Valid Combinations
Am29F002T-55
Am29F002B-55
Am29F002NT-55
Am29F002NB-55
PC, JC, JI, EC, EI
Am29F002T-70
Am29F002B-70
Am29F002NT-70
Am29F002NB-70
PC, PI, JC, JI, EC, EI
Am29F002T-90
Am29F002B-90
Am29F002NT-90
Am29F002NB-90
PC, PI, PE,
JC, JI, JE,
EC, EI, EE
Am29F002T-120
Am29F002B-120
Am29F002NT-120
Am29F002NB-120
Am29F002/Am29F002N
7
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29F002/Am29F002N Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
0.5 V, X = Don't Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See "Reading Array Data" for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
"sector address" consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7DQ0. Standard read cycle timings apply in this
mode. Refer to the "Autoselect Mode" and Autoselect
Command Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The "AC
Characteristics" section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to "Write Operation
Operation
CE#
OE#
WE#
RESET#
(n/a Am29F002N)
A0A17
DQ0DQ7
Read
L
L
H
H
A
IN
D
OUT
Write
L
H
L
H
A
IN
D
IN
CMOS Standby
V
CC
0.5 V
X
X
H
X
High-Z
TTL Standby
H
X
X
H
X
High-Z
Output Disable
L
H
H
H
X
High-Z
Reset (n/a on Am29F002N)
X
X
X
L
X
High-Z
Temporary Sector Unprotect
(See Note)
X
X
X
V
ID
X
X
8
Am29F002/Am29F002N
P R E L I M I N A R Y
Status" for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins (CE# only on the Am29F002N) are
both held at V
CC
0.5 V. (Note that this is a more re-
stricted voltage range than V
IH
.) The device enters the
TTL standby mode when CE# and RESET# pins (CE#
only on the Am29F002N) are both held at V
IH
. The de-
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, "RE-
SET#: Hardware Reset Pin".
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, I
CC3
represents the
standby current specification.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics tables represents the
standby current specification.
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002N.
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
IL
, the device enters
the TTL standby mode; if RESET# is held at V
SS
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Table 2.
Am29F002/Am29F002N Top Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
X
X
X
64
00000h0FFFFh
SA1
0
1
X
X
X
64
10000h1FFFFh
SA2
1
0
X
X
X
64
20000h2FFFFh
SA3
1
1
0
X
X
32
30000h37FFFh
SA4
1
1
1
0
0
8
38000h39FFFh
SA5
1
1
1
0
1
8
3A000h3BFFFh
SA6
1
1
1
1
X
16
3C000h3FFFFh
Am29F002/Am29F002N
9
P R E L I M I N A R Y
Table 3.
Am29F002/Am29F002N Bottom Boot Block Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires V
ID
(11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Autoselect Codes (High Voltage Method) table. In addi-
tion, when verifying sector protection, the sector ad-
dress must appear on the appropriate highest order
address bits. Refer to the corresponding Sector Ad-
dress Tables. The Command Definitions table shows
the remaining address bits that are don't care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in the Command Defini-
tions table. This method does not require V
ID
. See
"Command Definitions" for details on using the autose-
lect mode.
Table 4.
Am29F002/Am29F002N Autoselect Codes (High Voltage Method)
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don't care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The
hardware sector unprotection feature re-enables both
program and erase operations in previously pro-
tected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure re-
quires a high voltage (V
ID
) on address pin A9 and the
control pins. Details on this method are provided in the
supplements, publication numbers 20819 and 21183.
Sector
A17
A16
A15
A14
A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal)
SA0
0
0
0
0
X
16
00000h03FFFh
SA1
0
0
0
1
0
8
04000h05FFFh
SA2
0
0
0
1
1
8
06000h07FFFh
SA3
0
0
1
X
X
32
08000h0FFFFh
SA4
0
1
X
X
X
64
10000h1FFFFh
SA5
1
0
X
X
X
64
20000h2FFFFh
SA6
1
1
X
X
X
64
30000h3FFFFh
Description
CE#
OE#
WE#
A17
to
A13
A12
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
Manufacturer ID: AMD
L
L
H
X
X
V
ID
X
L
X
L
L
01h
Device ID:
Am29F002/Am29F002N
(Top Boot Block)
L
L
H
X
X
V
ID
X
L
X
L
H
B0h
L
L
H
Device ID:
Am29F002/Am29F002N
(Bottom Boot Block)
L
L
H
X
X
V
ID
X
L
X
L
H
34h
L
L
H
Sector Protection Verification
L
L
H
SA
X
V
ID
X
L
X
H
L
01h
(protected)
00h
(unprotected)
10
Am29F002/Am29F002N
P R E L I M I N A R Y
Contact an AMD representative to obtain a copy of the
appropriate document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD's ExpressFlashTM Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See "Autoselect Mode" for details.
Temporary Sector Unprotect
Note: This feature requites the RESET# pin and is
therefore not available on the Am29F002N.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unprotect mode is activated by setting the
RESET# pin to V
ID
. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20818C-4
Am29F002/Am29F002N
11
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values
or writing them in the im-
proper sequence
resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
"AC Characteristics" section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See "Erase Sus-
pend/Erase Resume Commands" for more information
on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the "Reset Com-
mand" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
Method) table, which is intended for PROM program-
mers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence.
A read cycle at address XX00h or retrieves the manu-
facturer code. A read cycle at address XX01h returns
the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
sector is protected, or 00h if it is unprotected. Refer to
the Sector Address tables for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two un-
lock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program al-
gorithm. The system is
not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the pro-
grammed cell margin. The Command Definitions take
shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7
or DQ6. See "Write Operation Status" for information
on these status bits.
12
Am29F002/Am29F002N
P R E L I M I N A R Y
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. On the
Am29F002 only, note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a "0" back to a "1".
Attempting to do so may halt
the operation and set DQ5 to "1", or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still "0". Only erase operations can convert a "0"
to a "1".
Note: See the appropriate Command Definitions table for
program command sequence.
Figure 2.
Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does
not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. The Command
Definitions table shows the address and data require-
ments for the chip erase command sequence.
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. On the Am29F002
only, note that a hardware reset during the sector
erase operation immediately terminates the operation.
The Sector Erase command sequence should be rein-
itiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See "Write
Operation Status" for information on these status
bits. When the Embedded Erase algorithm is com-
plete, the device returns to reading array data and
addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in "AC
Characteristics" for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does
not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50
s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50
s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
20818C-5
Am29F002/Am29F002N
13
P R E L I M I N A R Y
commands can be assumed to be less than 50
s, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data.
The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the "DQ3: Sector Erase
Timer" section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. On the Am29F002 only, note that a hard-
ware reset
during the sector erase operation immedi-
ately terminates the operation. The Sector Erase
command sequence should be reinitiated once the de-
vice has returned to reading array data, to ensure data
integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
Refer to "Write Operation Status" for information on
these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the "AC Characteristics" section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Notes:
1. See the appropriate Command Definitions table for erase
command sequence.
2. See "DQ3: Sector Erase Timer" for more information.
Figure 3.
Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Data = FFh?
No
Yes
Erasure Completed
Embedded
Erase
algorithm
in progress
20818C-6
14
Am29F002/Am29F002N
P R E L I M I N A R Y
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50
s time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are "don't-cares" when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20
s to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device "erase
suspends" all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See "Write Operation Status" for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See "Write Operation Status" for more informa-
tion.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See "Autoselect Command Sequence"
for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Am29F002/Am29F002N
15
P R E L I M I N A R Y
Table 5.
Am29F002/Am29F002N Command Definitions
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17A13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
are write operations.
4. Address bits A17A12 are don't cares for unlock and
command cycles, except when PA or SA is required.
5. No unlock or command cycles required when reading array
data.
6. The Reset command is required to return to reading array
data when device is in the autoselect mode, or if DQ5 goes
high (while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a
read cycle.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. See "Autoselect Command Sequence" for
more information.
9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a
sector erase operation.
10. The Erase Resume command is valid only during the Erase
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 24)
First
Second Third Fourth Fifth Sixth
Addr
Data
Addr
Data
Addr
Data Addr
Data
Addr Data
Addr
Data
Read (Note 5)
1
RA
RD
Reset (Note 6)
1
XXX
F0
Auto-
select
(Note 7)
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID,
Top Boot Block
4
555
AA
2AA
55
555
90
X01
B0
Device ID,
Bottom Boot Block
4
555
AA
2AA
55
555
90
X01
34
Sector Protect Verify
(Note 8)
4
555
AA
2AA
55
555
90
(SA)
X02
00
01
Program
4
555
AA
2AA
55
555
A0
PA
PD
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 9)
1
XXX
B0
Erase Resume (Note 10)
1
XXX
30
Cy
c
les
16
Am29F002/Am29F002N
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
sys tem w he th er a n E m be dd e d Alg or ith m is i n
progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
g r a m m i n g d u r i n g E r a s e S u s p e n d . W h e n t h e
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 2
s, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a "0" on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a "1" on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to "1";
prior to this, the device outputs the "complement," or
"0." The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100
s, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0DQ6 while
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
the "AC Characteristics" section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 4 shows the Data# Polling algorithm.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7DQ0
Addr = VA
Read DQ7DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = "1" because
DQ7 may change simultaneously with DQ5.
20818C-7
Figure 4.
Data# Polling Algorithm
Am29F002/Am29F002N
17
P R E L I M I N A R Y
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100
s, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2
s after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the
"AC Characteristics" section for the timing diagram.
The DQ2 vs. DQ6 figure shows the differences be-
tween DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs
for DQ2 and DQ6.
Figure 5 shows the toggle bit algorithm in flowchart
form, and the section "DQ2: Toggle Bit II" explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the dif-
ferences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 5 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The sys-
tem can read array data on DQ7DQ0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not complete the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 5).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a "1." This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
18
Am29F002/Am29F002N
P R E L I M I N A R Y
The DQ5 failure condition may appear if the system
tries to program a "1" to a location that is previously pro-
grammed to "0." Only an erase operation can change
a "0" back to a "1."
Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a "1."
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from "0" to "1." The system may ignore DQ3
if the system can guarantee that the time between ad-
ditional sector erase commands will always be less
than 50
s. See also the "Sector Erase Command Se-
quence" section.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is "1", the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is "0", the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Read DQ7DQ0
Toggle Bit
= Toggle?
Read DQ7DQ0
Twice
Read DQ7DQ0
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to "1". See text.
20818C-8
Figure 5.
Toggle Bit Algorithm
(Notes
1, 2)
(Note 1)
Am29F002/Am29F002N
19
P R E L I M I N A R Y
Table 6.
Write Operation Status
Notes:
1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See "DQ5: Exceeded Timing Limits" for more information.
Operation
DQ7
(Note 1)
DQ6
DQ5
(Note 2)
DQ3
DQ2
(Note 1)
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspend
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
20
Am29F002/Am29F002N
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . 65
C to +150
C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . 55
C to +125
C
Voltage with Respect to Ground
V
CC
(Note 1) . . . . . . . . . . . . . . . . 2.0 V to +7.0 V
A9, OE#, and
RESET# (Note 2). . . . . . . . . . . . 2.0 V to +12.5 V
All other pins (Note 1) . . . . . . . . . 0.5 V to +7.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, input or I/O pins may undershoot V
SS
to 2.0 V for periods of up to 20 ns. See Figure 6.
Maximum DC voltage on input or I/O pins is
V
CC
+0.5 V.
During voltage transitions, input or I/O pins may overshoot
to V
CC
+2.0 V for periods up to 20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is 0.5 V. During voltage transitions, A9, OE#, and
RESET# may undershoot V
SS
to 2.0 V for periods of up
to 20 ns. See Figure 6. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to +13.5 V for periods
up to 20 ns. (RESET# is not available on Am29F002N.)
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 6.
Maximum Negative Overshoot
Waveform
Figure 7.
Maximum Positive Overshoot
Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . . 0C to +70C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . . 40C to +85C
Extended (E) Devices
Ambient Temperature (T
A
) . . . . . . . . 55C to +125C
V
CC
Supply Voltages
V
CC
for 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
V
CC
for 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
20818C-9
20 ns
20 ns
V
CC
+2.0 V
V
CC
+0.5 V
20 ns
2.0 V
20818C-10
Am29F002/Am29F002N
21
P R E L I M I N A R Y
DC CHARACTERISTICS
TTL/NMOS Compatible
Notes:
1. RESET# is not available on Am29F002N.
2. The I
CC
current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
3. I
CC
active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
, V
CC
= V
CC
max
1.0
A
I
LIT
A9, OE#, RESET# Input Load Current
(Notes 1, 4)
V
CC
= V
CC max
;
A9, OE#, RESET# = 12.5 V
50
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
, V
CC
= V
CC max
1.0
A
I
CC1
V
CC
Active Read Current (Note 2)
CE# = V
IL,
OE#
=
V
IH
20
30
mA
I
CC2
V
CC
Active Write Current (Notes 3, 4)
CE# = V
IL,
OE#
=
V
IH
30
40
mA
I
CC3
V
CC
Standby Current
V
CC
= V
CC max
, CE#, OE# = V
IH
0.4
1
mA
I
CC4
V
CC
Reset Current (Note 1)
V
CC
= V
CC max
; RESET# = V
IL
0.4
1
mA
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.5
V
V
ID
Voltage for Autoselect and Temporary
Sector Unprotect
V
CC
= 5.0 V
11.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 12 mA, V
CC
= V
CC min
0.45
V
V
OH
Output High Voltage
I
OH
= 2.5 mA, V
CC
= V
CC min
2.4
V
V
LKO
Low V
CC
Lock-Out Voltage
3.2
4.2
V
22
Am29F002/Am29F002N
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. RESET# is not available on Am29F002N.
2. The I
CC
current listed is typically less than 2 mA/MHz, with OE# at V
IH
.
3. I
CC
active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. I
CC3
and I
CC4
= 20
A max at extended temperature (>+85
C).
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Load Current
V
IN
= V
SS
to V
CC
,
V
CC
= V
CC
max
1.0
A
I
LIT
A9, OE#, RESET#
Input Load Current (Notes 1, 4)
V
CC
= V
CC max
;
A9, OE#, RESET# = 12.5 V
50
A
I
LO
Output Leakage Current
V
OUT
= V
SS
to V
CC
,
V
CC
= V
CC max
1.0
A
I
CC1
V
CC
Active Read Current
(Note 2)
CE# = V
IL,
OE#
=
V
IH
20
30
mA
I
CC2
V
CC
Active Write Current
(Notes 3, 4)
CE# = V
IL,
OE#
=
V
IH
30
40
mA
I
CC3
V
CC
Standby Current (Note 5)
V
CC
= V
CC max
; CE# = V
CC
0.5 V
1
5
A
I
CC4
V
CC
Reset Current (Notes 1, 5)
V
CC
= V
CC max
; RESET# = V
IL
1
5
A
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
0.7 x V
CC
V
CC
+ 0.3
V
V
ID
Voltage for Autoselect and
Temporary Sector Unprotect
V
CC
= 5.0 V
11.5
12.5
V
V
OL
Output Low Voltage
I
OL
= 12 mA, V
CC
= V
CC min
0.45
V
V
OH1
Output High Voltage
I
OH
= 2.5 mA, V
CC
= V
CC min
0.85 V
CC
V
V
OH2
I
OH
= 100
A, V
CC
= V
CC min
V
CC
0.4
V
LKO
Low V
CC
Lock-Out Voltage
3.2
4.2
V
Am29F002/Am29F002N
23
P R E L I M I N A R Y
TEST CONDITIONS
Table 7.
Test Specifications
KEY TO SWITCHING WAVEFORMS
2.7 k
CL
6.2 k
5.0 V
Device
Under
Test
20818C-11
Figure 8.
Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition
-55
All
others
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
5
20
ns
Input Pulse Levels
0.03.0
0.452.4
V
Input timing measurement
reference levels
1.5 0.8,
2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
KS000010-PAL
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
24
Am29F002/Am29F002N
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 8 and Table 7 for test specifications.
Parameter
Description
Speed Option
JEDEC
Std
Test Setup
-55
-70
-90
-120
Unit
t
AVAV
t
RC
Read Cycle Time (Note 1)
Min
55
70
90
120
ns
t
AVQV
t
ACC
Address to Output Delay
CE# = V
IL
OE# = V
IL
Max
55
70
90
120
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
55
70
90
120
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
30
30
35
50
ns
t
EHQZ
t
DF
Chip Enable to Output High Z (Note 1)
Max
15
20
20
30
ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Note 1)
Max
15
20
20
30
ns
t
OEH
Output Enable
Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE#
or OE#, Whichever Occurs First (Note 1)
Min
0
ns
t
CE
Outputs
WE#
Addresses
CE#
OE#
HIGH Z
Output Valid
HIGH Z
Addresses Stable
t
RC
t
ACC
t
OEH
t
OE
RESET#
n/a Am29F002N
t
DF
t
OH
20818C-12
Figure 9.
Read Operations Timings
25
Am29F002/Am29F002N
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Note: Not 100% tested. RESET# is not available on Am29F002N.
Parameter
Description
All Speed Options
JEDEC
Std
Test Setup
Unit
t
READY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
s
t
READY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
t
RP
RESET# Pulse Width
Min
500
ns
t
RH
RESET# High Time Before Read (See Note)
Min
50
ns
RESET#
n/a Am29F002N
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
CE#, OE#
t
RH
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002N
t
RP
20818C-13
Figure 10.
RESET# Timings
Am29F002/Am29F002N
26
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Parameter
-55
-70
-90
-120
JEDEC
Std.
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
55
70
90
120
ns
t
AVWL
t
AS
Address Setup Time
Min
0
ns
t
WLAX
t
AH
Address Hold Time
Min
45
45
45
50
ns
t
DVWH
t
DS
Data Setup Time
Min
25
30
45
50
ns
t
WHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHWL
t
GHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
ELWL
t
CS
CE# Setup Time
Min
0
ns
t
WHEH
t
CH
CE# Hold Time
Min
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
30
35
45
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min
20
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
t
VCS
V
CC
Setup Time (Note 1)
Min
50
s
27
Am29F002/Am29F002N
P R E L I M I N A R Y
AC CHARACTERISTICS
OE#
WE#
CE#
V
CC
Data
Addresses
t
DS
t
AH
t
DH
t
WP
PD
t
WHWH1
t
WC
t
AS
t
WPH
t
VCS
555h
PA
PA
Read Status Data (last two cycles)
A0h
t
GHWL
t
CS
Status
D
OUT
Program Command Sequence (last two cycles)
t
CH
PA
Notes:
1. PA = program address, PD = program data, D
OUT
is the true data at the program address.
20818C-14
Figure 11.
Program Operation Timings
Am29F002/Am29F002N
28
P R E L I M I N A R Y
AC CHARACTERISTICS
OE#
CE#
Addresses
V
CC
WE#
Data
2AAh
SA
t
GHWL
t
AH
t
WP
t
WC
t
AS
t
WPH
555h for chip erase
10 for Chip Erase
30h
t
DS
t
VCS
t
CS
t
DH
55h
t
CH
In
Progress
Complete
t
WHWH2
VA
VA
Erase Command Sequence (last two cycles)
Read Status Data
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status").
20818C-15
Figure 12.
Chip/Sector Erase Operation Timings
29
Am29F002/Am29F002N
P R E L I M I N A R Y
AC CHARACTERISTICS
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0DQ6
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
20818C-16
Figure 13.
Data# Polling Timings (During Embedded Algorithms)
WE#
CE#
OE#
High Z
t
OE
DQ6/DQ2
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
t
ACC
t
RC
Valid Data
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Valid Status
VA
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
20818C-17
Figure 14.
Toggle Bit Timings (During Embedded Algorithms)
Am29F002/Am29F002N
30
P R E L I M I N A R Y
AC CHARACTERISTICS
Temporary Sector Unprotect (Am29F002 only)
Note: Not 100% tested.
Parameter
All Speed Options
JEDEC
Std.
Description
Unit
t
VIDR
V
ID
Rise and Fall Time (See Note)
Min
500
ns
t
RSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
s
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
20818C-18
Figure 15.
DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embedded
Erasing
RESET#
t
VIDR
12 V
0 or 5 V
CE#
WE#
RY/BY#
t
VIDR
t
RSP
Program or Erase Command Sequence
0 or 5 V
20818C-19
Figure 16.
Temporary Sector Unprotect Timing Diagram (Am29F002 only)
31
Am29F002/Am29F002N
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
Parameter
-55
-70
-90
-120
JEDEC
Std.
Description
Unit
t
AVAV
t
WC
Write Cycle Time (Note 1)
Min
55
70
90
120
ns
t
AVEL
t
AS
Address Setup Time
Min
0
ns
t
ELAX
t
AH
Address Hold Time
Min
45
45
45
50
ns
t
DVEH
t
DS
Data Setup Time
Min
25
30
45
50
ns
t
EHDX
t
DH
Data Hold Time
Min
0
ns
t
OES
Output Enable Setup Time
Min
0
ns
t
GHEL
t
GHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
t
WLEL
t
WS
WE# Setup Time
Min
0
ns
t
EHWH
t
WH
WE# Hold Time
Min
0
ns
t
ELEH
t
CP
CE# Pulse Width
Min
30
35
45
50
ns
t
EHEL
t
CPH
CE# Pulse Width High
Min
20
ns
t
WHWH1
t
WHWH1
Programming Operation (Note 2)
Typ
7
s
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 2)
Typ
1
sec
Am29F002/Am29F002N
32
P R E L I M I N A R Y
AC CHARACTERISTICS
t
GHEL
t
WS
OE#
CE#
WE#
RESET#
t
DS
Data
t
AH
Addresses
t
DH
t
CP
DQ7#
D
OUT
t
WC
t
AS
t
CPH
PA
Data# Polling
A0 for program
55 for erase
t
RH
t
WHWH1 or 2
t
WH
PD for program
30 for sector erase
10 for chip erase
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, D
OUT
= data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
20818C-20
Figure 17.
Alternate CE# Controlled Write Operation Timings
33
Am29F002/Am29F002N
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25
C, 5.0 V V
CC
, 100,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90C, V
CC
= 4.5 V (4.75 V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 100,000 cycles.
LATCHUP CHARACTERISTICS
Note: Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time. RESET# not available on Am29F002N.
TSOP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25C, f = 1.0 MHz.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
1
8
s
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
7
s
Byte Programming Time
7
300
s
Excludes system level
overhead (Note 5)
Chip Programming Time (Note 3)
1.8
5.4
s
Description
Min
Max
Input voltage with respect to V
SS
on all pins except I/O pins
(including A9, OE#, and RESET#)
1.0 V
12.5 V
Input voltage with respect to V
SS
on all I/O pins
1.0 V
V
CC
+ 1.0 V
V
CC
Current
100 mA
+100 mA
Parameter
Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
6
7.5
pF
C
OUT
Output Capacitance
V
OUT
= 0
8.5
12
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
7.5
9
pF
Am29F002/Am29F002N
34
P R E L I M I N A R Y
PLCC AND PDIP PIN CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25
C, f = 1.0 MHz.
DATA RETENTION
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
4
6
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
Control Pin Capacitance
V
PP
= 0
8
12
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
C
10
Years
125
C
20
Years
35
Am29F002/Am29F002N
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PD 032
32-Pin Plastic DIP (measured in inches)
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.670
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160
.016
.022
SEATING PLANE
.015
.060
16-038-S_AG
PD 032
EC75
5-28-97 lv
32
17
16
.630
.700
0
10
.600
.625
.009
.015
.050 REF.
.026
.032
TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF.
.490
.530
Am29F002/Am29F002N
36
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TS 032
32-Pin Standard Thin Small Package (measured in millimeters)
Pin 1 I.D.
1
18.30
18.50
7.90
8.10
0.50 BSC
0.05
0.15
0.95
1.05
16-038-TSOP-2
TS 032
DA95
3-25-97 lv
19.80
20.20
1.20
MAX
0.50
0.70
0.10
0.21
0
5
0.08
0.20
37
Am29F002/Am29F002N
P R E L I M I N A R Y
REVISION SUMMARY FOR AM29F002/AM29F002N
Revision C
Global
Made formatting and layout consistent with other data
sheets. Used updated common tables and diagrams.
Combined Am29F002 and Am29F002N into a single
data sheet.
Revision C+1
Figure 17, Alternate CE# Controlled Write
Operations Timings
Removed the RY/BY# waverform and t
BUSY
parameter.
The RY/BY# pin is not available on this device.
Revision C+2
Block Diagram
Corrected diagram by adding paths from the timer to
the PGM and Erase Voltage Generators.
Table 3, Bottom Boot Block Sector Addresses
Corrected adddress bit A15 for sector SA2 to "0."
Table 5, Command Definitions
Deleted the lower row of addresses in the Sector Pro-
tect Verify command definitions.
In the legend, corrected the definition for SA to indicate
that address bits A17A13 uniquely select a sector.
Deleted Note 4.
DC Characteristics
Added Note 4 reference to I
LIT
. Corrected maximum
currents for I
CC1
and I
CC2
, typical currents for I
CC3
and
I
CC4
, test conditions for I
CC4
and V
OL
.
In TTL/NMOS table, deleted Note 5.
In CMOS table, corrected I
OH
current for V
OH
.
AC Characteristics
Read Operations: Corrected t
DF
specifications for -55
speed option.
Erase/Program Operations: Corrected the notes refer-
ence for t
WHWH1
and t
WHWH2
. These parameters are
100% tested. Corrected the note reference for t
VCS
.
This parameter is not 100% tested. Removed -150
specifications. Corrected t
DS
and t
WP
for -55 speed op-
tion, t
AH
for -90 speed option.
Alternate CE# Controlled Erase/Program Operations:
Corrected the notes reference for t
WHWH1
and t
WHWH2
.
These parameters are 100% tested. This parameter is
not 100% tested. Removed -150 specifications. Cor-
rected t
DS
and t
CP
for -55 speed option.
Temporary Sector Unprotect Table
Added note reference for t
VIDR
. This parameter is not
100% tested.
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Copyright 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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