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Datasheet: 28F256 (Advanced Micro Devices)

256 Kilobit (32 K X 8-bit) Cmos 12.0 Volt, Bulk Erase Flash Memory

 

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Advanced Micro Devices

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FINAL
Publication# 11560
Rev: G Amendment/+2
Issue Date: January 1998
Am28F256
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
High performance
-- 70 ns maximum access time
s
CMOS Low power consumption
-- 30 mA maximum active current
-- 100 A maximum standby current
-- No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
-- 32-pin PDIP
-- 32-pin PLCC
-- 32-pin TSOP
s
10,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
5%
s
Latch-up protected to 100 mA
from 1 V to V
CC
+1 V
s
Flasherase
Electrical Bulk Chip-Erase
-- One second typical chip-erase
s
Flashrite Programming
-- 10 s typical byte-program
-- 0.5 second typical chip program
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
-- Low cost single transistor memory cell
s
Automatic write/erase pulse stop timer
GENERAL DESCRIPTION
The Am28F256 is a 256 K Flash memory organized as
32 Kbytes of 8 bits each. AMD's Flash memories offer
the most cost-effective and reliable read/write non-
volatile random access memory. The Am28F256 is
packaged in 32-pin PDIP, PLCC, and TSOP versions. It
is designed to be reprogrammed and erased in-system
or in standard EPROM programmers. The Am28F256
is erased when shipped from the factory.
The standard Am28F256 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F256 has separate chip enable (CE
#
) and
output enable (OE
#
) controls.
AMD's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256 uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
power supply levels during erase and programming.
AMD's Flash technology reliably stores memor y
contents even after 10,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The Am28F256
uses a 12.0V
5% V
PP
high voltage input to perform
the Flasherase
and Flashrite
algorithms.
The highest degree of latch-up protection is achieved
with AMD's proprietar y non-epi process. Latch-up
protection is provided for stresses up to 100 milliamps
on address and data pins from 1 V to V
CC
+1 V.
The Am28F256 is byte programmable using 10 s
programming pulses in accordance with AMD 's
Flashrite programming algorithm. The typical room
temperature programming time of the Am28F256 is a
half a second. The entire chip is bulk erased using
10 ms erase pulses according to AMD's Flasherase
alrogithm. Typical erasure at room temperature is
accomplished in less than one second. The windowed
package and the 15-20 minutes required for EPROM
erasure using ultra-violet light are eliminated.
2
Am28F256
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F256 is designed to support either WE
#
or CE
#
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of WE
#
or CE
#
whichever occurs last. Data is latched on the rising edge
of WE
#
or CE
#
whichever occurs first. To simplify the fol-
lowing discussion, the WE
#
pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the WE
#
signal.
AMD's Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256 electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
BLOCK DIAGRAM
PRODUCT SELECTOR GUIDE
Family Part Number
Am28F256
Speed Options (V
CC
= 5.0 V
10%)
-70
-90
-120
-150
-200
Max Access Time (ns)
70
90
120
150
200
CE# (E#) Access (ns)
70
90
120
150
200
OE# (G#) Access (ns)
35
35
50
55
55
Erase
Voltage
Switch
Command
Register
Program
Voltage
Switch
Chip Enable
Output Enable
Logic
Y-Decoder
X-Decoder
Y-Gating
262,144
Bit
Cell Matrix
11560F-1
A0A14
OE#
CE#
WE#
VSS
VCC
To Array
DQ0DQ7
Input/Output
Buffers
Data
Latch
VPP
Address
Latch
Low VCC
Detector
Program/Erase
Pulse Timer
State
Control
Am28F256
3
CONNECTION DIAGRAMS
V
PP
V
CC
DQ0
A5
A12
A14
1
3
5
7
9
11
12
10
2
4
8
6
32
30
28
26
24
14
21
23
31
29
25
27
NC
A7
13
22
20
19
A6
15
16
18
17
A4
A3
A2
A1
A0
DQ1
DQ2
V
SS
WE# (W#)
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
DQ6
DQ5
DQ4
DQ3
11560F-2
PDIP
NC
NC
Note: Pin 1 is marked for orientation.
DQ6
V
PP
DQ5
DQ4
DQ3
1
31 30
2
3
4
5
6
7
8
9
10
11
12
13
17 18 19 20
16
15
14
29
28
27
26
25
24
23
22
21
32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE# (G#)
A10
CE# (E#)
DQ7
A12
NC
NC
V
CC
WE# (W#)
NC
DQ1
DQ2
V
SS
PLCC
11560F-3
4
Am28F256
CONNECTION DIAGRAMS (continued)
LOGIC SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin TSOP--Standard Pinout
A11
A9
A8
A13
A14
NC
WE#
V
CC
V
PP
NC
NC
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
D7
D6
D5
D4
D3
V
SS
D2
D1
D0
A0
A1
A2
A3
32-Pin TSOP--Reverse Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
NC
WE#
V
CC
V
PP
NC
NC
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
D7
D6
D5
D4
D3
V
SS
D2
D1
D0
A0
A1
A2
A3
11560G-4
15
8
DQ0
A0A14
CE# (E#)
OE# (G#)
DQ7
WE# (W#)
11560F-5
Am28F256
5
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of:
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
DEVICE NUMBER/DESCRIPTION
Am28F256
256 Kilobit (32 K x 8-Bit) CMOS Flash Memory
AM28F256
-70
J
C
OPTIONAL PROCESSING
Blank = Standard Processing
B
= Burn-In
Contact an AMD representative for more information.
TEMPERATURE RANGE
C = Commercial (0C to +70C)
I = Industrial (40C to +85C)
E = Extended (55C to +125C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
B
Valid Combinations
AM28F256-70
PC, PI, PE,
JC, JI, JE,
EC, EI, EE,
FC, FI, FE
AM28F256-90
AM28F256-120
AM28F256-150
AM28F256-200
6
Am28F256
PIN DESCRIPTION
A0A14
A
ddress Inputs for memory locations. Internal latches
hold addresses during write cycles.
CE
#
(E
#
)
Chip Enable active low input activates the chip's control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.
DQ0DQ7
Data Inputs during memor y write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE
#
(G
#
)
Output Enable active low input gates the outputs of the
device through the data buffers dur ing memor y
read cycles. Output Enable is high during command
sequencing and program/erase operations.
V
CC
Power supply for device operation. (5.0 V
5% or 10%)
V
PP
Program voltage input. V
PP
must be at high voltage in
order to write to the command register. The command
register controls all functions required to alter the
memory array contents. Memory contents cannot be
altered when V
PP
V
CC
+2 V.
V
SS
Ground
WE
#
(W
#
)
Write Enable active low input controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the
Write Enable pulse and the appropriate data is latched
on the rising edge of the pulse. Write Enable high
inhibits writing to the device.
Am28F256
7
BASIC PRINCIPLES
The device uses 100% TTL-level control inputs to
manage the command register. Erase and repro-
gramming operations use a fixed 12.0 V
5% high
voltage input.
Read Only Memory
Without high V
PP
voltage, the device functions as a
read only memor y and operates like a standard
EPROM. The control inputs still manage traditional
read, standby, output disable, and Auto select modes.
Command Register
The command register is enabled only when high volt-
age is applied to the V
PP
pin. The erase and repro-
gramming operations are only accessed via the
register. In addition, two-cycle commands are required
for erase and reprogramming operations. The tradi-
tional read, standby, output disable, and Auto select
modes are available via the register.
The device's command register is written using stan-
dard microprocessor write timings. The register con-
trols an internal state machine that manages all device
operations. For system design simplification, the de-
vice is designed to support either WE# or CE# con-
trolled writes. During a system write cycle, addresses
are latched on the falling edge of WE# or CE# which-
ever occurs last. Data is latched on the rising edge of
WE# or CE# whichever occur first. To simplify the fol-
lowing discussion, the WE# pin is used as the write
cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# sig-
nal.
Overview of Erase/Program Operations
FlasheraseTM Sequence
A multiple step command sequence is required to
erase the Flash device (a two-cycle Erase command
and repeated one cycle verify commands).
Note: The Flash memory array must be completely
programmed to 0's prior to erasure. Refer to the
FlashriteTM Programming Algorithm.
1. Erase Setup: Write the Setup Erase command to
the command register.
2. Erase: Write the Erase command (same as Setup
Erase command) to the command register again.
The second command initiates the erase operation.
The system software routines must now time-out
the erase pulse width (10 ms) prior to issuing the
Erase-verify command. An integrated stop timer
prevents any possibility of overerasure.
3. Erase-Verify: Write the Erase-verify command to
the command register. This command terminates
the erase operation. After the erase operation,
each byte of the array must be verified. Address in-
formation must be supplied with the Erase-verify
command. This command verifies the margin and
outputs the addressed byte in order to compare the
a r r a y d a t a w i t h F F h d a t a ( B y t e e r a s e d ) .
After successful data verification the Erase-verify
command is written again with new address infor-
mation. Each byte of the array is sequentially veri-
fied in this manner.
If data of the addressed location is not verified, the
Erase sequence is repeated until the entire array is
successfully verified or the sequence is repeated
1000 times.
Flashrite
Programming Sequence
A three step command sequence (a two-cycle Program
command and one cycle Verify command) is required
to program a byte of the Flash array. Refer to the Flash-
rite
Algorithm.
1. Program Setup: Write the Setup Program com-
mand to the command register.
2. Program: Write the Program command to the com-
mand register with the appropriate Address and
Data. The system software routines must now time-
out the program pulse width (10 s) prior to issuing
the Program-verify command. An integrated stop
timer prevents any possibility of overprogramming.
3. Program-Verify: Write the Program-verify com-
mand to the command register. This command ter-
minates the programming operation. In addition,
this command verifies the margin and outputs the
byte just programmed in order to compare the array
data with the original data programmed. After suc-
cessful data verification, the programming se-
quence is initiated again for the next byte address to
be programmed.
If data is not verified successfully, the Program se-
quence is repeated until a successful comparison is
verified or the sequence is repeated 25 times.
Data Protection
The device is designed to offer protection against acci-
dental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. The device powers up in its read only state. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful comple-
tion of specific command sequences.
The device also incorporates several features to pre-
vent inadvertent write cycles resulting from V
CC
power-
up and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up
and power-down, the device locks out write cycles for
8
Am28F256
V
CC
< V
LKO
(see DC Characteristics section for
voltages). When V
CC
< V
LKO
, the command register is
disabled, all inter nal program/erase circuits are
disabled, and the device resets to the read mode. The
device ignores all writes until V
CC
> V
LKO
. The user
must ensure that the control pins are in the correct logic
state when V
CC
> V
LKO
to prevent uninitentional writes.
Write Pulse "Glitch" Protection
Noise pulses of less than 10 ns (typical) on OE#, CE#
or WE# will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE# = V
IL
, CE#
= V
IH
or WE# = V
IH
. To initiate a write cycle CE# and
WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE# = CE# = V
IL
and
OE# = V
IH
will not accept commands on the rising
edge of WE#. The internal state machine is automat-
ically reset to the read mode on power-up.
FUNCTIONAL DESCRIPTION
Description Of User Modes
Table 1.
Am28F256 Device Bus Operations (Notes 7 and 8)
Legend:
X = Don't care, where Don't Care is either V
IL
or V
IH
levels. V
PPL
= V
PP
<
V
CC
+ 2 V. See DC Characteristics for voltage levels
of V
PPH
. 0 V < An < V
CC
+ 2 V, (normal TTL or CMOS input levels, where n = 0 or 9).
Notes:
1. V
PPL
may be grounded, connected with a resistor to ground, or < V
CC
+ 2.0 V. V
PPH
is the programming voltage specified for
the device. Refer to the DC characteristics. When V
PP
= V
PPL
, memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 2.
3. 11.5 < V
ID
< 13.0 V. Minimum V
ID
rise time and fall time (between 0 and V
ID
voltages) is 500 ns.
4. Read operation with V
PP
= V
PPH
may access array data or the Auto select codes.
5. With V
PP
at high voltage, the standby current is I
CC
+ I
PP
(standby).
6. Refer to Table 3 for valid D
IN
during a write operation.
7. All inputs are Don't Care unless otherwise stated, where Don't Care is either V
IL
or V
IH
levels. In the Auto select mode all
addresses except A
9
and A
0
must be held at V
IL
.
8. If V
CC
1.0 Volt, the voltage difference between V
PP
and V
CC
should not exceed 10.0 volts. Also, the Am28F256 has a V
PP
rise time and fall time specification of 500 ns minimum.
Operation
CE#
(E#)
OE#
(G#)
WE#
(W#)
V
PP
(Note 1)
A0
A9
I/O
Read-Only
Read
V
IL
V
IL
X
V
PPL
A0
A9
D
OUT
Standby
V
IH
X
X
V
PPL
X
X
HIGH Z
Output Disable
V
IL
V
IH
V
IH
V
PPL
X
X
HIGH Z
Auto-select Manufacturer
Code (Note 2)
V
IL
V
IL
V
IH
V
PPL
V
IL
V
ID
(Note 3)
CODE
(01h)
Auto-select Device
Code (Note 2)
V
IL
V
IL
V
IH
V
PPL
V
IH
V
ID
(Note 3)
CODE
(A1h)
Read/Write
Read
V
IL
V
IL
V
IH
V
PPH
A0
A9
D
OUT
(Note 4)
Standby (Note 5)
V
IH
X
X
V
PPH
X
X
HIGH Z
Output Disable
V
IL
V
IH
V
IH
V
PPH
X
X
HIGH Z
Write
V
IL
V
IH
V
IL
V
PPH
A0
A9
D
IN
(Note 6)
Am28F256
9
READ ONLY MODE
When V
PP
is less than V
CC
+ 2 V, the command register
is inactive. The device can either read array or autose-
lect data, or be standby mode.
Read
The device functions as a read only memory when V
PP
< V
CC
+ 2 V.
The device has two control functions. Both
must be satisfied in order to output data. CE# controls
power to the device. This pin should be used for spe-
cific device selection. OE# controls the device outputs
and should be used to gate data to the output pins if a
device is selected.
Address access time t
ACC
is equal to the delay from
stable addresses to valid output data. The chip enable
access time t
CE
is the delay from stable addresses and
stable CE# to valid data at the output pins. The output
enable access time is the delay from the falling edge of
OE# to valid data at the output pins (assuming the ad-
dresses have been stable at least t
ACC
t
OE
).
Standby Mode
The device has two standby modes. The CMOS
standby mode (CE# input held at V
CC
0.5 V), con-
sumes less than 100 A of current. TTL standby mode
(CE# is held at V
IH
) reduces the current requirements
to less than 1mA. When in the standby mode the out-
puts are in a high impedance state, independent of the
OE# input.
If the device is deselected during erasure, program-
ming, or program/erase verification, the device will
draw active current until the operation is terminated.
Output Disable
Output from the device is disabled when OE# is at a
logic high level. When disabled, output pins are in a
high impedance state.
Auto Select
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
The Auto select mode allows the reading out of a binary
code from the device that will identify its manufacturer
and type. This mode is intended for the purpose
of automatically matching the device to be pro-
grammed with its corresponding programming algo-
r ith m. Th is mo de is f unc tio nal ove r t he en tir e
temperature range of the device.
Programming In A PROM Programmer
To activate this mode, the programming equipment
must force V
ID
(11.5 V to 13.0 V) on address A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A
0
from V
IL
to V
IH
. All other
address lines must be held at V
IL
, and V
PP
must
be
less than or equal to V
CC
+ 2.0 V while using this Auto
select mode. Byte 0 (A0 = V
IL
) represents the manufac-
turer code and byte 1 (A0 = V
IH
) the device identifier
code. For the device these two bytes are given in Table
2 below. All identifiers for manufacturer and device
codes will exhibit odd parity with the MSB (DQ7) de-
fined as the parity bit.
Table 2.
Am28F256 Auto Select Code
Type
A0
Code
(HEX)
Manufacturer Code
V
IL
01
Device Code
V
IH
A1
10
Am28F256
ERASE, PROGRAM, AND READ MODE
When V
PP
is equal to 12.0 V 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must be applied to the V
PP
pin in order to
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an addressable
memory location. The register is a latch that stores the
command, along with the address and data information
needed to execute the command. The register is written
by bringing WE# and CE# to V
IL
, while OE# is at V
IH
.
Addresses are latched on the falling edge of WE#, while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
The device requires the OE# pin to be V
IH
for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be V
IH
, and CE# and WE#
must be V
IL
. If any pin is not in the correct state a write
command will not be executed.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the V
PP
pin. The device operates as a read only mem-
ory. High voltage on the V
PP
pin enables the command
register. Device operations are selected by writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.
Read Command
Memory contents can be accessed via the read com-
mand when V
PP
is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon V
PP
power-up. The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V
PP
power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
Table 3.
Am28F256 Command Definitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don't care.
Addresses are latched on the falling edge of the WE# pulse.
3. RD = Data read from location RA during read operation.
EVD = Data read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE#.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
4. Refer to the appropriate section for algorithms and timing diagrams.
Command (Note 4)
First Bus Cycle
Second Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Read Memory
Write
X
00h/FFh
Read
RA
RD
Read Auto select
Write
X
80h or 90h
Read
00h/01h
01h/A1h
Erase Set-up/Erase Write
Write
X
20h
Write
X
20h
Erase-Verify
Write
EA
A0h
Read
X
EVD
Program Setup/Program
Write
X
40h
Write
PA
PD
Program-Verify
Write
X
C0h
Read
X
PVD
Reset Write
X
FFh
Write
X
FFh
Am28F256
11
FLASHERASE
ERASE SEQUENCE
Erase Setup
Erase Setup is the first of a two-cycle erase command.
It is a command-only operation that stages the device
for bulk chip erase. The array contents are not altered
with this command. 20h is written to the command reg-
ister in order to perform the Erase Setup operation.
Erase
The second two-cycle erase command initiates the
bulk erase operation. You must write the Erase com-
mand (20h) again to the register. The erase operation
begins with the rising edge of the WE# pulse. The
erase operation must be terminated by writing a new
command (Erase-verify) to the register.
This two step sequence of the Setup and Erase com-
mands helps to ensure that memory contents are not
accidentally erased. Also, chip erasure can only occur
when high voltage is applied to the V
PP
pin and all con-
trol pins are in their proper state. In absence of this high
voltage, memory contents cannot be altered. Refer to
AC Erase Characteristics and Waveforms for specific
timing parameters.
Note: The Flash memory device must be fully
programmed to 00h data prior to erasure. This
equalizes the charge on all memory cells ensuring
reliable erasure.
Erase-Verify Command
The erase operation erases all bytes of the array
in parallel. After the erase operation, all bytes must be
sequentially verified. The Erase-verify operation is initi-
ated by writing A0h to the register. The byte address to
be verified must be supplied with the command. Ad-
dresses are latched on the falling edge of the WE#
pulse or CE# pulse, whichever occurs later. The rising
edge of the WE# pulse terminates the erase operation.
Margin Verify
During the Erase-verify operation, the device applies
an int er na lly g en erat ed ma rg in vo lta ge to th e
addressed byte. Reading FFh from the addressed byte
indicates that all bits in the byte are properly erased.
Verify Next Address
You must write the Erase-verify command with the ap-
propriate address to the register prior to verification of
each address. Each new address is latched on the fall-
ing edge of WE# or CE# pulse, whichever occurs later.
The process continues for each byte in the memory
array until a byte does not return FFh data or all the
bytes in the array are accessed and verified.
If an address is not verified to FFh data, the entire chip
is erased again (refer to Erase Setup/Erase). Erase
verification then resumes at the address that failed to
verify. Erase is complete when all bytes in the array
have been verified. The device is now ready to be pro-
grammed. At this point, the verification operation is ter-
minated by writing a valid command (e.g. Program
Setup) to the command register. Figure 1 and Table 4,
the Flasherase
electrical erase algorithm, illustrate how
commands and bus operations are combined to per-
form electrical erasure. Refer to AC Erase Characteris-
tics and Waveforms for specific timing parameters.
12
Am28F256
Figure 1.
Flasherase
Electrical Erase Algorithm
Start
Program All Bytes to 00h
Apply V
PPH
Address = 00h
PLSCNT = 0
Write Erase Setup Command
Write Erase Command
Time out 10 ms
Write Erase Verify
Time out 6 s
Read Data from Device
Data = FFh
Last Address
Write Reset Command
Apply V
PPL
Erasure Completed
PLSCNT =
1000
Increment Address
Apply V
PPL
Erase Error
No
Yes
No
11559G-6
Yes
Yes
Yes
No
No
Increment
PLSCNT
Data = 00h
Am28F256
13
FLASHERASE
ELECTRICAL ERASE ALGORITHM
This Flash memory device erases the entire array in
parallel. The erase time depends on V
PP
, temperature,
and number of erase/program cycles on the device. In
general, reprogramming time increases as the number
of erase/program cycles increases.
The Flasherase electrical erase algorithm employs an
interactive closed loop flow to simultaneously erase all
bits in the array. Erasure begins with a read of the mem-
ory contents. The device is erased when shipped from
the factory. Reading FFh data from the device would
immediately be followed by executing the Flashrite pro-
gramming algorithm with the appropriate data pattern.
Should the device be currently programmed, data other
than FFh will be returned from address locations.
Follow the Flasherase algorithm. Uniform and reliable
erasure is ensured by first programming all bits in the
device to their charged state (Data = 00h). This is
accomplished using the Flashr ite Programming
algorithm. Erasure then continues with an initial erase
operation. Erase verification (Data = FFh) begins at
address 0000h and continues through the array to the
la s t a d d r e s s, o r u n t i l d a t a o t h e r t h a n F F h i s
encountered. If a byte fails to verify, the device is
er as e d ag a in . W i th ea ch er as e o pe r at io n , a n
increasing number of bytes verify to the erased state.
Typically, devices are erased in less than 100 pulses
(one second). Erase efficiency may be improved by
storing the address of the last byte that fails to verify in
a register. Following the next erase operation,
verification may start at the stored address location. A
total of 1000 erase pulses are allowed per reprogram
cycle, which corresponds to approximately 10 seconds
of cumulative erase time. The entire sequence of erase
and byte verification is performed with high voltage
applied to the V
PP
pin. Figure 1 illustrates the electrical
erase algorithm.
Table 4.
Flasherase
Electrical Erase Algorithm
Notes:
1. See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
switchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2.0 V.
2. Erase Verify is performed only after chip erasure. A final read compare may be performed (optional) after the register is written
with the read command.
3. The erase algorithm Must Be Followed to ensure proper and reliable operation of the device.
Bus Operations
Command
Comments
Entire memory must = 00h before erasure (Note 3)
Note: Use Flashrite
programming algorithm (Figure 3) for
programming.
Standby
Wait for V
PP
Ramp to V
PPH
(Note 1)
Initialize:
Addresses
PLSCNT (Pulse count)
Write
Erase Setup
Data = 20h
Erase
Data = 20h
Standby
Duration of Erase Operation (t
WHWH2
)
Write
Erase-Verify (Note 2)
Address = Byte to Verify
Data = A0h
Stops Erase Operation
Standby
Write Recovery Time before Read = 6 s
Read
Read byte to verify erasure
Standby
Compare output to FFh
Increment pulse count
Write
Reset
Data = FFh, reset the register for read operations
Standby
Wait for V
PP
Ramp to V
PPL
(Note 1)
14
Am28F256
Figure 2.
AC Waveforms For Erase Operations
ANALYSIS OF ERASE TIMING WAVEFORM
Note: This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite
Programming algorithm.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.
The erase pulse occurs in section C.
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
After each erase operation each byte must be verified.
The byte address to be verified must be supplied with
Addresses
CE
#
OE
#
WE
#
Data
V
PP
V
CC
11559G-7
20h
20h
Section
A0h
Data
Out
Bus Cycle
Write
Write
Time-out
Write
Time-out
Read
Standby
Command
20h
20h
N/A
A0h
N/A
Compare
Data
N/A
Function
Erase
Setup
Erase
Erase
(10 ms)
Erase-
Verify
Transition
(6 s)
Erase
Verification
Proceed per
Erase
Algorithm
A
B
D
E
F
C
G
A
B
D
E
F
C
G
Am28F256
15
the Erase-verify command (section D). Addresses are
latched on the falling edge of the WE# pulse.
Another software timing routine (6 s duration) must be
executed to allow for generation of internal voltages for
margin checking and read operation (section E).
During Erase-verification (section F) each address that
returns FFh data is successfully erased. Each address
of the array is sequentially verified in this manner by re-
peating sections D thru F until the entire array is veri-
fied or an address fails to verify. Should an address
location fail to verify to FFh data, erase the device
again. Repeat sections A thru F. Resume verification
(section D) with the failed address.
Each data change sequence allows the device to use
up to 1,000 erase pulses to completely erase. Typically
100 erase pulses are required.
Note: All address locations must be programmed to
00h prior to erase. This equalizes the charge on all
memory cells and ensures reliable erasure.
FLASHRITE PROGRAMMING SEQUENCE
Program Setup
The device is programmed byte by byte. Bytes may be
programmed sequentially or at random. Program Setup
is the first of a two-cycle program command. It stages
the device for byte programming. The Program Setup
operation is performed by writing 40h to the command
register.
Program
Only after the program Setup operation is completed
will the next WE# pulse initiate the active programming
operation. The appropriate address and data for pro-
gramming must be available on the second WE# pulse.
Addresses and data are internally latched on the falling
and rising edge of the WE# pulse respectively. The ris-
ing edge of WE# also begins the programming opera-
tion. You must write the Program-verify command to
terminate the programming operation. This two step
sequence of the Setup and Program commands helps
to ensure that memory contents are not accidentally
written. Also, programming can only occur when high
voltage is applied to the V
PP
pin and all control pins are
in their proper state. In absence of this high voltage,
memory contents cannot be programmed.
Refer to AC Characteristics and Waveforms for specific
timing parameters.
Program Verify Command
Following each programming operation, the byte just
programmed must be verified.
Write C0h into the command register in order to initiate
the Program-verify operation. The rising edge of this
WE pulse terminates the programming operation. The
Program-verify operation stages the device for verifica-
tion of the last byte programmed. Addresses were pre-
viously latched. No new information is required.
Margin Verify
During the Program-verify operation, the device applies
an internally generated margin voltage to the ad-
dressed byte. A normal microprocessor read cycle out-
puts the data. A successful comparison between the
programmed byte and the true data indicates that the
byte was successfully programmed. The original pro-
grammed data should be stored for comparison. Pro-
gramming then proceeds to the next desired byte
location. Should the byte fail to verify, reprogram (refer
to Program Setup/Program). Figure 3 and Table 5 indi-
cate how instructions are combined with the bus oper-
ations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for spe-
cific timing parameters.
Flashrite
Programming Algorithm
The device Flashrite
Programming algorithm employs
an interactive closed loop flow to program data byte by
byte. Bytes may be programmed sequentially or at ran-
dom. The Flashrite
Programming algorithm uses 10 s
programming pulses. Each operation is followed by a
byte verification to determine when the addressed byte
has been successfully programmed. The program al-
gorithm allows for up to 25 programming operations per
byte per reprogramming cycle. Most bytes verify after
the first or second pulse. The entire sequence of pro-
gramming and byte verification is performed with high
voltage applied to the V
PP
pin. Figure 3 and Table 5 il-
lustrate the programming algorithm.
16
Am28F256
Figure 3.
Flashrite
Programming Algorithm
Start
Apply V
PPH
PLSCNT = 0
Write Program Setup Command
Write Program Command (A/D)
Time out 10 s
Write Program Verify Command
Time out 6 s
Read Data from Device
Last Address
Write Reset Command
Apply V
PPL
Programming Completed
PLSCNT =
25?
Increment Address
Apply V
PPL
Device Failed
No
11559G-8
Yes
Yes
No
No
Verify Byte
Increment PLSCNT
Yes
Am28F256
17
Table 5.
Flashrite Programming Algorithm
Notes:
1. See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
switchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2.0 V.
2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register
is written with the read command.
Bus Operations
Command
Comments
Standby
Wait for V
PP
Ramp to V
PPH
(Note 1)
Initialize Pulse counter
Write
Program Setup
Data = 40h
Program
Valid Address/Data
Standby
Duration of Programming Operation (t
WHWH1
)
Write
Program-Verify (Note 2)
Data = C0h Stops Program Operation
Standby
Write Recovery Time before Read = 6 s
Read
Read Byte to Verify Programming
Standby
Compare Data Output to Data Expected
Write
Reset
Data = FFh, resets the register for read operations.
Standby
Wait for V
PP
Ramp to V
PPL
(Note 1)
18
Am28F256
Figure 4.
AC Waveforms for Programming Operations
ANALYSIS OF PROGRAM TIMING WAVEFORMS
Program Setup/Program
Two-cycle write commands are required for program
operations (section A and B). The first program com-
mand (40h) is a Setup command and does not affect
the array data (section A). The second program com-
mand latches address and data required for program-
ming on the falling and rising edge of WE# respectively
(section B). The rising edge of this WE# pulse (section
B) also initiates the programming pulse. The device is
programmed on a byte by byte basis either sequentially
or randomly.
The program pulse occurs in section C.
Time-Out
A software timing routine (10 s duration) must be initi-
ated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibility
of overprogramming by limiting each time-out period of
10 s.
Program-Verify
Upon completion of the program timing routine, the mi-
croprocessor must write the program-verify command
(C0h). This command terminates the programming op-
eration on the rising edge of the WE# pulse (section D).
The program-verify command also stages the device
for data verification (section F). Another software timing
routine (6 s duration) must be executed to allow for
Addresses
CE
#
OE
#
WE
#
Data
V
PP
V
CC
11559G-9
Data
In
20h
Section
A0h
Data
Out
Bus Cycle
Write
Write
Time-out
Write
Time-out
Read
Standby
Command
40h
Program
Address,
Program Data
N/A
C0h
(Stops
Program)
N/A
Compare
Data
N/A
Function
Program
Setup
Program
Command
Latch
Address and
Data
Program
(10 s)
Program
Verify
Transition
(6 s)
Program
Verification
Proceed per
Programming
Algorithm
A
B
D
E
F
C
G
A
B
D
E
F
C
G
Am28F256
19
generation of internal voltages for margin checking and
read operations (section E).
During program-verification (section F) each byte just
programmed is read to compare array data with original
program data. When successfully verified, the next de-
sired address is programmed. Should a byte fail to ver-
ify, reprogram the byte (repeat section A thru F). Each
data change sequence allows the device to use up to
25 program pulses per byte. Typically, bytes are verified
within one or two pulses.
Algorithm Timing Delays
There are four different timing delays associated with
the Flasherase
and Flashrite
algorithms:
1. The first delay is associated with the V
PP
rise-time
when V
PP
first turns on. The capacitors on the V
PP
bus cause an RC ramp. After switching on the V
PP
,
the delay required is proportional to the number of
devices being erased and the 0.1 mF/device. V
PP
must reach its final value 100 ns before commands
are executed.
2. The second delay time is the erase time pulse width
(10 ms). A software timing routine should be run by
the local microprocessor to time out the delay. The
erase operation must be terminated at the conclu-
sion of the timing routine or prior to executing any
system interrupts that may occur during the erase
operation. To ensure proper device operation, write
the Erase-verify operation after each pulse.
3. A third delay time is required for each programming
pulse width (10 ms). The programming algorithm is
interactive and verifies each byte after a program
pulse. The program operation must be terminated at
the conclusion of the timing routine or prior to exe-
cuting any system interrupts that may occur during
the programming operation.
4. A fourth timing delay associated with both the
Flasherase and Flashrite algorithms is the write re-
covery time (6 ms). During this time internal circuitry
is changing voltage levels from the erase/ program
level to those used for margin verify and read oper-
ations. An attempt to read the device during this pe-
riod will result in possible false data (it may appear
the device is not properly erased or programmed).
Note: Software timing routines should be written in
machine language for each of the delays. Code written
in machine language requires knowledge of the appro-
priate microprocessor clock speed in order to accu-
rately time each delay.
Parallel Device Erasure
Many applications will use more than one Flash
memory device. Total erase time may be minimized by
implementing a parallel erase algorithm. Flash
memories may erase at different rates. Therefore each
device must be verified separately. When a device is
completely erased and verified use a masking code to
prevent further erasure. The other devices will continue
to erase until verified. The masking code applied could
be the read command (00h).
Power-Up/Power-Down Sequence
The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V
CC
1.0 Volt, the voltage difference between V
PP
and V
CC
should not exceed 10.0 Volts. Also, the device has V
PP
rise time and fall time specification of 500 ns minimum.
Reset Command
The Reset command initializes the Flash memory de-
vice to the Read mode. In addition, it also provides the
user with a safe method to abort any device operation
(including program or erase).
The Reset command must be written two consecutive
times after the setup Program command (40h). This will
reset the device to the Read mode.
Following any other Flash command write the Reset
command once to the device. This will safely abort any
previous operation and initialize the device to the
Read mode.
The Setup Program command (40h) is the only com-
mand that requires a two sequence reset cycle. The
first Reset command is interpreted as program data.
However, FFh data is considered null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical "1" to "0"). The second Reset
command safely aborts the programming operation
and resets the device to the Read mode.
Memory contents are not altered in any case.
This detailed information is for your reference. It may
prove easier to always issue the Reset command two
consecutive times. This eliminates the need to deter-
mine if you are in the setup Program state or not.
Programming In-System
Flash memories can be programmed in-system or in a
standard PROM programmer. The device may be sol-
dered to the circuit board upon receipt of shipment and
programmed in-system. Alternatively, the device may
initially be programmed in a PROM programmer prior
to soldering the device to the board.
20
Am28F256
Auto Select Command
AMD's Flash memories are designed for use in applica-
tions where the local CPU alters memory contents. Ac-
cordingly, manufacturer and device codes must be
accessible while the device resides in the target sys-
tem. PROM programmers typically access the signa-
ture codes by raising A9 to a high voltage. However,
multiplexing high voltage onto address lines is not a
generally desired system design practice.
The device contains an Auto Select operation to sup-
plement traditional PROM programming methodology.
The operation is initiated by writing 80h or 90h into the
command register. Following this command, a read
cycle address 0000h retrieves the manufacturer code
of 01h. A read cycle from address 0001h returns the
device code. To terminate the operation, it is necessary
to write another valid command, such as Reset (FFh),
into the register.
Am28F256
21
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . 65
C to +150
C
Plastic Packages . . . . . . . . . . . . . . . 65
C to +125
C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .55
C to + 125
C
Voltage with Respect To Ground
All pins except A9 and V
PP
(Note 1) . 2.0 V to +7.0 V
V
CC
(Note 1). . . . . . . . . . . . . . . . . . . . 2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V
V
PP
(Note 2). . . . . . . . . . . . . . . . . . . 2.0 V to +14.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During
voltage transitions, inputs may overshoot V
SS
to 2.0 V for
periods of up to 20 ns. Maximum DC voltage on input and
I/O pins is V
CC
+ 0.5 V. During voltage transitions, input
and I/O pins may overshoot to V
CC
+ 2.0 V for periods up
to 20 ns.
2. Minimum DC input voltage on A9 and V
PP
pins is 0.5 V.
During voltage transitions, A9 and V
PP
may overshoot
V
SS
to 2.0 V for periods of up to 20 ns. Maximum DC
input voltage on A9 and V
PP
is +13.0 V which may
overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output shorted to ground at a time. Du-
ration of the short circuit should not be greater than one
second.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for extended
periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
). . . . . . . . . . . .0
C to +70
C
Industrial (I) Devices
Ambient Temperature (T
A
). . . . . . . . . .40
C to +85
C
Extended (E) Devices
Ambient Temperature (T
A
). . . . . . . . .55
C to +125
C
V
CC
Supply Voltages
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . +4.50 V to +5.50 V
V
PP
Voltages
Read . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to +12.6 V
Program, Erase, and Verify . . . . . . +11.4 V to +12.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
22
Am28F256
MAXIMUM OVERSHOOT
Maximum Negative Input Overshoot
Maximum Positive Input Overshoot
Maximum V
PP
Overshoot
11560F-10
20 ns
20 ns
+0.8 V
0.5 V
20 ns
2.0 V
11560F-11
20 ns
V
CC
+ 0.5 V
2.0 V
20 ns
20 ns
V
CC
+ 2.0 V
11560F-12
20 ns
13.5 V
V
CC
+ 0.5 V
20 ns
20 ns
14.0 V
Am28F256
23
DC CHARACTERISTICS over operating range unless otherwise specified
TTL/NMOS Compatible
Notes:
1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied. If V
CC
1.0 Volt,
the voltage difference between V
PP
and V
CC
should not exceed 10.0 Volts. Also, the Am28F256 has a V
PP
rise time and fall
time specification of 500 ns minimum.
2. I
CC1
is tested with OE# = V
IH
to simulate open outputs.
3. Maximum active power usage is the sum of I
CC
and I
PP
..
4. Not 100% tested.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Leakage Current
V
CC
= V
CC
Max, V
IN
= V
CC
or V
SS
1.0
A
I
LO
Output Leakage Current
V
CC
= V
CC
Max, V
OUT
= V
CC
or V
SS
1.0
A
I
CCS
V
CC
Standby Current
V
CC
= V
CC
Max, CE# = V
IH
0.2
1.0
mA
I
CC1
V
CC
Active Read Current
V
CC =
V
CC
Max, CE# = V
IL,
OE# = V
IH
I
OUT
= 0 mA, at 6 MHz
20
30
mA
I
CC2
V
CC
Programming Current
CE#
=
V
IL
Programming in Progress (Note 4)
20
30
mA
I
CC3
V
CC
Erase Current
CE#
=
V
IL
Erasure in Progress (Note 4)
20
30
mA
I
PPS
V
PP
Standby Current
V
PP
= V
PPL
1.0
A
I
PP1
V
PP
Read Current
V
PP
= V
PPH
70
200
A
V
PP
= V
PPL
1.0
I
PP2
V
PP
Programming Current
V
PP
= V
PPH
Programming in Progress (Note 4)
10
30
mA
I
PP3
V
PP
Erase Current
V
PP
= V
PPH
Erasure in Progress (Note 4)
10
30
mA
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8 mA, V
CC
= V
CC
Min
0.45
V
V
OH1
Output High Voltage
I
OH
= 2.5 mA, V
CC
= V
CC
Min
2.4
V
V
ID
A9 Auto Select Voltage
A9 = V
ID
11.5
13.0
V
I
ID
A9 Auto Select Current
A9 = V
ID
Max, V
CC
= V
CC
Max
5
50
A
V
PPL
V
PP
during Read-Only
Operations
Note: Erase/Program are inhibited
when V
PP
= V
PPL
0.0
V
CC
+2.0
V
V
PPH
V
PP
during Read/Write
Operations
11.4
12.6
V
V
LKO
Low V
CC
Lock-out Voltage
3.2
3.7
V
24
Am28F256
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. Caution: The Am28F256 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied. If V
CC
1.0 volt,
the voltage difference between V
PP
and V
CC
should not exceed 10.0 volts. Also, the Am28F256 has a V
PP
rise time and fall
time specification of 500 ns minimum.
2. I
CC1
is tested with OE# = V
IH
to simulate open outputs.
3. Maximum active power usage is the sum of I
CC
and I
PP
.
4. Not 100% tested.
Parameter
Symbol
Parameter Description
Test Conditions
Min
Typ
Max
Unit
I
LI
Input Leakage Current
V
CC
= V
CC
Max, V
IN
= V
CC
or V
SS
1.0
A
I
LO
Output Leakage Current
V
CC
= V
CC
Max, V
OUT
= V
CC
or V
SS
1.0
A
I
CCS
V
CC
Standby Current
V
CC
= V
CC
Max, CE#
= V
CC
+ 0.5 V
15
100
A
I
CC1
V
CC
Active Read Current
V
CC
= V
CC
Max, CE# = V
IL,
OE# = V
IH
I
OUT
= 0 mA, at 6 MHz
20
30
mA
I
CC2
V
CC
Programming Current
CE# = V
IL
Programming in Progress (Note 4)
20
30
mA
I
CC3
V
CC
Erase Current
CE# = V
IL
Erasure in Progress (Note 4)
20
30
mA
I
PPS
V
PP
Standby Current
V
PP
= V
PPL
1.0
A
I
PP1
V
PP
Read Current
V
PP
= V
PPH
70
200
A
I
PP2
V
PP
Programming Current
V
PP
= V
PPH
Programming in Progress (Note 4)
10
30
mA
I
PP3
V
PP
Erase Current
V
PP
= V
PPH
Erasure in Progress (Note 4)
10
30
mA
V
IL
Input Low Voltage
0.5
0.8
V
V
IH
Input High Voltage
0.7 V
CC
V
CC
+ 0.5
V
V
OL
Output Low Voltage
I
OL
= 5.8 mA, V
CC
= V
CC
Min
0.45
V
V
OH1
Output High Voltage
I
OH
= 2.5 mA, V
CC
= V
CC
Min
0.85 V
CC
V
V
OH2
I
OH
= 100 A, V
CC
= V
CC
Min
V
CC
0.4
V
ID
A9 Auto Select Voltage
A9 = V
ID
11.5
13.0
V
I
ID
A9 Auto Select Current
A9 = V
ID
Max, V
CC
= V
CC
Max
5
50
A
V
PPL
V
PPL
during Read-Only
Operations
Note: Erase/Program are inhibited
when V
PP
= V
PPL
0.0
V
CC
+ 2.0
V
V
PPH
V
PP
during Read/Write
Operations
11.4
12.6
V
V
LKO
Low V
CC
Lock-out Voltage
3.2
3.7
V
Am28F256
25
Figure 5.
Am28F256--Average I
CC
Active vs. Frequency
V
CC
= 5.5 V, Addressing Pattern = Minmax
Data Pattern = Checkerboard
TEST CONDITIONS
Table 6.
Test Specifications
I
CC
Active
in mA
25
20
15
10
5
0
0
1
2
3
4
5
6
7
8
9
10
11
12
Frequency in MHz
11560F-13
55
C
0
C
25
C
70
C
125
C
2.7 k
CL
6.2 k
5.0 V
Device
Under
Test
11560G-14
Figure 6.
Test Setup
Note: Diodes are IN3064 or equivalent
Test Condition
-70
All others
Unit
Output Load
1 TTL gate
Output Load Capacitance, C
L
(including jig capacitance)
30
100 pF
Input Rise and Fall Times
10
ns
Input Pulse Levels
0.03.0
0.452.4
V
Input timing measurement
reference levels
1.5
0.8, 2.0
V
Output timing measurement
reference levels
1.5
0.8, 2.0
V
26
Am28F256
SWITCHING TEST WAVEFORMS
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC Characteristics--Read Only Operation
Notes:
1. Guaranteed by design not tested.
2. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F256 Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
t
AVAV
t
RC
Read Cycle Time (Note 2)
Min
70
90
120
150
200
ns
t
ELQV
t
CE
Chip Enable AccessTime
Max
70
90
120
150
200
ns
t
AVQV
t
ACC
Address Access Time
Max
70
90
120
150
200
ns
t
GLQV
t
OE
Output Enable Access Time
Max
35
35
50
55
55
ns
t
ELQX
t
LZ
Chip Enable to Output in Low Z
(Note 2)
Min
0
0
0
0
0
ns
t
EHQZ
t
DF
Chip Disable to Output in High Z
(Note 1)
Max
20
20
30
35
35
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
(Note 2)
Min
0
0
0
0
0
ns
t
GHQZ
t
DF
Output Disable to Output in High Z
(Note 2)
Max
20
20
30
35
35
ns
t
AXQX
t
OH
Output Hold from first of Address,
CE#, or OE# Change (Note 2)
Min
0
0
0
0
0
ns
t
WHGL
Write Recovery Time before Read
Min
6
6
6
6
6
s
t
VCS
V
CC
Setup Time to Valid Read
(Note 2)
Min
50
50
50
50
50
s
11560G-15
3 V
0 V
Input
Output
1.5 V
1.5 V
Test Points
AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic "1" and 0 V for a logic "0". Input pulse rise and fall times
are
10 ns.
2.4 V
0.45 V
Input
Output
Test Points
2.0 V
2.0 V
0.8 V
0.8 V
AC Testing (all speed options except -70): Inputs are driven at
2.4 V for a logic "1" and 0.45 V for a logic "0". Input pulse rise
and fall times are
10 ns.
Am28F256
27
AC Characteristics--Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
4. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F256 Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
t
AVAV
t
WC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
t
AVWL
t
AS
Address Set-up Time
Min
0
0
0
0
0
ns
t
WLAX
t
AH
Address Hold Time
Min
45
45
50
60
75
ns
t
DVWH
t
DS
Data Setup Time
Min
45
45
50
50
50
ns
t
WHDX
t
DH
Data Hold Time
Min
10
10
10
10
10
ns
t
WHGL
t
WR
Write Recovery Time
before Read
Min
6
6
6
6
6
s
t
GHWL
Read Recovery Time
before Write
Min
0
0
0
0
0
s
t
ELWL
t
CS
Chip Enable Set-up Time
Min
0
0
0
0
0
ns
t
WHEH
t
CH
Chip Enable Hold Time
Min
0
0
0
0
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
45
45
50
60
60
ns
t
WHWL
t
WPH
Write Pulse
Width HIGH
Min
20
20
20
20
20
ns
t
WHWH1
Duration of Programming
Operation (Note 2)
Min
10
10
10
10
10
s
t
WHWH2
Duration of
Erase Operation (Note 2)
Min
9.5
9.5
9.5
9.5
9.5
ms
t
VPEL
V
PP
Setup Time to
Chip Enable LOW (Note 4)
Min
100
100
100
100
100
ns
t
VCS
V
CC
Set-up Time to
Chip Enable LOW (Note 4)
Min
50
50
50
50
50
s
t
VPPR
V
PP
Rise Time
90% V
PPH
(Note 4)
Min
500
500
500
500
500
ns
t
VPPF
V
PP
Fall Time
10% V
PPL
(Note 4)
Min
500
500
500
500
500
ns
t
LKO
V
CC
< V
LKO
to Reset (Note 4)
Min
100
100
100
100
100
ns
28
Am28F256
KEY TO SWITCHING WAVEFORMS
SWITCHING WAVEFORMS
Figure 7.
AC Waveforms for Read Operations
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Addresses
CE# (E#)
OE# (G#)
WE# (W#)
Data (DQ)
5.0 V
V
CC
0 V
Power-up, Standby
Device and
Address Selection
Outputs
Enabled
Data
Valid
Standby, Power-Down
Addresses Stable
High Z
High Z
t
WHGL
t
AVQV
(t
ACC
)
t
EHQZ
(t
DF
)
t
GHQZ
(t
DF
)
t
ELQX
(t
LZ
)
t
GLQX
(t
OLZ
)
t
ELQV
(t
CE
)
t
GLQV
(t
OE
)
t
AXQX
(t
OH
)
Output Valid
t
AVAV
(t
RC
)
t
VCS
11560G-16
Am28F256
29
SWITCHING WAVEFORMS
Figure 8.
AC Waveforms for Erase Operations
DATA IN =
A0h
VALID
DATA
OUT
Erase-Verify
Command
Erase
Verification
Standby,
Power-down
t
WLAX
(t
AH
)
t
EHQZ
(t
DF
)
t
WHGL
t
GHQZ
(t
DF
)
t
GLQX
(t
OLZ
)
t
GLQV
(t
OE
)
t
ELQV
(t
CE
)
11560F-17
t
ELQX
(t
LZ
)
t
AVAV
(t
RC
)
t
AXQX
(t
OH
)
DATA IN
= 20h
DATA IN
= 20h
Setup Erase
Command
Erase
Command
Power-up,
Standby
t
AVWL
(t
AS
)
t
AVAV
(t
WC
)
t
ELWL
(t
CS
)
t
GHWL
(t
OES
)
t
WHEH
(t
CH
)
t
WHWH2
t
WHWL
(t
WPH
)
t
WHDX
(t
DH
)
t
WLWH
(t
WP
)
t
DVWH
(t
DS
)
t
VCS
t
VPEL
Addresses
HIGH Z
CE# (E#)
OE# (G#)
WE# (W#)
Data (DQ)
5.0 V
V
CC
0 V
V
PPH
V
PP
V
PPL
Erasure
30
Am28F256
SWITCHING WAVEFORMS
Figure 9.
AC Waveforms for Programming Operations
DATA IN
= C0h
VALID
DATA
OUT
Verify
Command
Programming
Verification
Standby,
Power-down
t
WLAX
(t
AH
)
t
GHQZ
(t
DF
)
t
WHGL
t
GHQZ
(t
DF
)
t
GLQX
(t
OLZ
)
t
GLQV
(t
OE
)
t
ELQV
(t
CE
)
11560F-18
t
ELQX
(t
LZ
)
t
AVAV
(t
RC
)
t
AXQX
(t
OH
)
DATA IN
= 40h
DATA IN
Setup Program
Command
Program
Command
Latch Address
and Data
Power-up,
Standby
t
AVWL
(t
AS
)
t
AVAV
(t
WC
)
t
ELWL
(t
CS
)
t
GHWL
(t
OES
)
t
WHEH
(t
CH
)
t
WHWH1
t
WHWL
(t
WPH
)
t
WHDX
(t
DH
)
t
WLWH
(t
WP
)
t
DVWH
(t
DS
)
t
VCS
t
VPEL
Addresses
HIGH Z
CE# (E#)
OE# (G#)
WE# (W#)
Data (DQ)
5.0 V
V
CC
0 V
V
PPH
V
PP
V
PPL
Programming
Am28F256
31
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. 25
C, 12 V V
PP
.
2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count
(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual
device limit.
LATCHUP CHARACTERISTICS
PIN CAPACITANCE
Note: Sampled, not 100% tested. Test conditions T
A
= 25C, f = 1.0 MHz.
DATA RETENTION
Parameter
Limits
Comments
Min
Typ
(Note 1)
Max
(Note 2)
Unit
Chip Erase Time
1
10
sec
Excludes 00h programming prior to erasure
Chip Programming Time
0.5
3
sec
Excludes system-level overhead
Write/Erase Cycles
10,000
Cycles
Min
Max
Input Voltage with respect to V
SS
on all pins except I/O pins (Including A9 and V
PP
)
1.0 V
13.5 V
Input Voltage with respect to V
SS
on all pins I/O pins
1.0 V
V
CC
+ 1.0 V
Current
100 mA
+100 mA
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
8
10
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
V
PP
Input Capacitance
V
PP
= 0
8
12
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
C
10
Years
125
C
20
Years
32
Am28F256
PHYSICAL DIMENSIONS
PD032--32-Pin Plastic DIP (measured in inches)
PL032--32-Pin Plastic Leaded Chip Carrier (measured in inches)
Pin 1 I.D.
1.640
1.670
.530
.580
.005 MIN
.045
.065
.090
.110
.140
.225
.120
.160
.016
.022
SEATING PLANE
.015
.060
16-038-S_AG
PD 032
EC75
5-28-97 lv
32
17
16
.630
.700
0
10
.600
.625
.009
.015
.050 REF.
.026
.032
TOP VIEW
Pin 1 I.D.
.485
.495
.447
.453
.585
.595
.547
.553
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SEATING
PLANE
.125
.140
.009
.015
.080
.095
.042
.056
.013
.021
.400
REF.
.490
.530
Am28F256
33
PHYSICAL DIMENSIONS
TS032--32-Pin Standard Thin Small Outline Package (measured in millimeters)
Pin 1 I.D.
1
18.30
18.50
7.90
8.10
0.50 B
0.05
0.15
0.95
1.05
16-038-TSOP-2
TS 032
DA95
3-25-97 lv
19.80
20.20
1.20
MAX
0.50
0.70
0.10
0.21
0
5
0.08
0.20
34
Am28F256
PHYSICAL DIMENSIONS
TSR032--32-Pin Reversed Thin Small Outline Package (measured in millimeters)
1
18.30
18.50
19.80
20.20
7.90
8.10
0.50 BSC
0.05
0.15
0.95
1.05
16-038-TSOP-2
TSR032
DA95
3-25-97 lv
Pin 1 I.D.
1.20
MAX
0.50
0.70
0.10
0.21
0
5
0.08
0.20
Am28F256
35
DATA SHEET REVISION SUMMARY FOR
AM28F256
Revision G
Deleted -75, -95, and -250 speed options. Matched for-
matting to other current data sheets.
Revision G+1
Figure 3, Flashrite Programming Algorithm: Moved end
of arrow originating from Increment Address box so
that it points to the PLSCNT = 0 box, not the Write Pro-
gram Verify Command box. This is a correction to the
diagram on page 6-189 of the 1998 Flash Memory
Data Book.
Revision G+2
Programming In A PROM Programmer:
Deleted the paragraph "(Refer to the AUTO SELECT
paragraph in the ERASE, PROGRAM, and READ
MODE section for programming the Flash memory de-
vice in-system)."
Trademarks
Copyright 1998 Advanced Micro Devices, Inc. All rights reserved.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
© 2019 • ICSheet
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