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Datasheet: S2072 (Applied Micro Circuits Corp.)

Four Port Bypass and Repeater For Fc-al

 

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1
FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
February 18, 2000 / Revision D
FEATURES
Micropower Bipolar Technology
ANSI X3T11 Fibre Channel Compliant
Monolithic Clock Recovery Unit
Retimes & Buffers Received Data
Jitter Peaking < 0.1 dB
Lock Detect Function
Frequency Detection
Four Port Bypass Circuits
Suitable for both Coaxial and Optical Link
Low Power Operation 0.93 W Typical
106.25 or 53.125 MHz Reference Clock
Compact 10 mm x 10 mm 64 Pin
PQFP Package
3.3 V Supply
APPLICATIONS
FC-AL Nodes
RAID
JBOD
SAN
GENERAL DESCRIPTION
The Four Port Bypass and Repeater for FC-AL Cir-
cuit is used in full-speed (1.0625 Gb/s) Disk Arrays.
It contains a monolithic Clock Recovery Unit (CRU),
a lock detect feature and four port bypass circuits.
The S2072 may be used to implement a single chip
Arbitrated Loop Port Bypass Retiming Node. The
Figure 1. S2072 Functional Block Diagram
DEVICE
SPECIFICATION
FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
S2072 performs the function of four port bypass cir-
cuits followed by a Clock and Data Retimer (CDR).
The CDR retimes incoming serial data, detects
whether a valid signal is present and outputs a low
jitter serial data stream.
FUNCTIONAL DESCRIPTION
The S2072 functional block diagram is shown in Fig-
ure 1. The S2072 performs two functions. The first
function is a Quad Port Bypass Circuit (PBC) for
nodes in a FC-AL system. The low jitter accumula-
tion of the port bypass path is essential in these
systems. The second function is to restore signal
quality in RAID drives using the FC-AL link configu-
ration. The S2072 clock and data recovery PLL pro-
vides low jitter transfer peaking and high jitter
tolerance. In addition, the lock detect circuit monitors
the incoming signals for frequency, which is useful
for link performance monitoring and detection of
channel present.
Jitter Performance
Input jitter tolerance is defined as the amplitude of
frequency dependent, random and deterministic jitter
that causes the clock recovery PLL to violate the
BER specifications.
The S2072 complies with the minimum jitter toler-
ance requirements proposed by the Fibre Channel
jitter working group when used with differential in-
puts and outputs as shown in Figure 2. In addition,
the S2072 is designed for minimum jitter generation
and jitter transfer specifications. This allows the opti-
mum system design for arbitrated loop architectures.
0
1
0
1
0
1
0
1
DDO0 DDI0
EN0
DDO1
DDI1
EN1
DDO2
DDI2
EN2
DDO3 DDI3
EN3
IN
CDR
OUTP/N
LOCKDET
BYPASS
REFCLK
LCKREFN
REFSEL
LPF1
LPF2
2
FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
February 18, 2000 / Revision D
Figure 2. FC-AL JBOD Application for Repeaters
CDR
0
1
0
1
0
1
0
1
Disk
Storage
FC-AL Disk Drive
LRC
Interlock
S2070
FC
XCVR
E_STORE
Disk
Storage
FC-AL Disk Drive
LRC
Interlock
E_STORE
Disk
Storage
FC-AL Disk Drive
LRC
Interlock
E_STORE
Optics
or
Copper
S2058
S2072
Dual
SC
or
DB-9
Normal
Normal
Normal
Bypass
Pulldown for Bypass in
Absence of Disk Drive
S2070
FC
XCVR
S2070
FC
XCVR
3
FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
February 18, 2000 / Revision D
DEVICE DESCRIPTION
The S2072 provides a port bypass function for up to 4
nodes in an FC-AL circuit, with low jitter accumulation.
An integrated repeater reduces jitter and restores sig-
nal amplitude levels for optimal signal integrity. Jitter
performance of the PLL is specified by jitter tolerance
and jitter transfer. In accordance with ANSI X3T11,
jitter tolerance is divided into random, deterministic,
and frequency dependent jitter. Figure 3 illustrates the
components of random, deterministic, and frequency
dependent jitter that must be tolerated to be ANSI
X3T11 compliant.
Frequency Dependent Jitter Tolerance
Frequency Dependent Input jitter tolerance is defined
as the peak to peak amplitude of sinusoidal jitter ap-
plied on the input signal that causes the clock recovery
to violate BER specifications. See Figure 4.
Random Jitter Tolerance
Random Jitter Tolerance is the amount of jitter with a
gaussian distribution that the clock recovery PLL must
tolerate.
Deterministic Jitter Tolerance
Deterministic Jitter Tolerance is the amount of Deter-
ministic jitter that the clock recovery PLL must tolerate.
Jitter transfer
Jitter transfer is defined as the ratio of jitter on the
output signal to the jitter applied on the input signal
versus frequency. Jitter transfer requirements are
shown in Figures 4 and 5. The measurement condition
is that input sinusoidal jitter up to the mask level in
Figure 4 is applied and the output jitter is measured for
compliance to the mask of Figure 5. The jitter transfer
mask includes specifications for both jitter peaking and
bandwidth.
Lock detect
The S2072 lock detect circuit monitors the selected
input signal to detect the presence of the channel. This
is done by monitoring the frequency content of the in-
coming data. The frequency monitor circuit checks the
difference between the divided down recovered clock
and the externally supplied reference clock (REFCLK).
If the frequency difference between the recovered
clock and the reference clock varies by more than
100 ppm the part will be declared out of lock. In the out
of lock state, the PLL will lock to the local reference
clock and periodically poll the serial data inputs looking
for data with valid frequency content.
Figure 3. Input Jitter Tolerance
Figure 5. Jitter Transfer Specification
Figure 4. Frequency Dependent Jitter
Tolerance Mask
FREQ DEP
DJ(ISI)
RJ
10
-12
0
329
612
940
PS
BER
f
c
/25,000
(42.5 kHz)
Cut-off Freq A
f
c
/1,667
(637 kHz)
Cut-off Freq B
TIME (Unit Interval - UI)
1.5
0.4
Frequency (Hz)
(kHz) = Cut-off Freq @ 1,0625 Gbps
Jitter
Transfer
Acceptable Range
slope = -20 dB/decade
fc = 2 MHz
Peaking = 0.2 dB
4
FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
February 18, 2000 / Revision D
Table 1. Pin Assignment and Descriptions
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FOUR PORT BYPASS AND REPEATER FOR FC-AL
S2072
February 18, 2000 / Revision D
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Table 1. Pin Assignment and Descriptions
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