Fibre Channel Specification
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet Specification and the ANSI X3T11 Fibre
Channel specification, and runs at 1062 Mbps or
1250 Mbps data rates with an associated 10-bit data
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates approximately 620 mW under typical
including Fibre Channel, serial backplanes, and pro-
prietary point-to-point links. Figure 1 shows a typical
configuration incorporating the chip.
ization and deserialization functions for block en-
coded data to implement a Gigabit Ethernet or Fibre
Channel interface. The S2070 functional block dia-
gram is depicted in Figure 2. The sequence of op-
erations is as follows:
2. Parallel-to-serial conversion
3. Serial output
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
from a DC-balanced encoding scheme, such as the
8B/10B transmission code, in which information to be
transmitted is encoded 8 bits at a time into 10-bit trans-
off-line testing. This is useful for ensuring the
integrity of the serial channel before enabling the
transmission medium. It also allows for system
Report RC 9391, May 1982.
data and serializes it for transmission over fiber optic
or coaxial cable media. The chip is fully compatible
with the IEEE 802.3z Gigabit Ethernet and ANSI
X3T11 Fibre Channel standards. The S2070 uses a
PLL to generate the serial rate transmit clock. The
transmitter runs at 10 times the TBC input clock, and
operates in either full rate or half rate mode.
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the trans-
mitter on the positive going edge of TBC. The data is
then clocked into the serial output shift register. The
shift register is clocked by the internally generated
bit clock which is 10x the TBC input frequency. TX
is transmitted first.
plied from a clock source with 100 ppm tolerance to
assure that the transmitted data meets the Fibre
Channel frequency limits. The internal serial clock is
frequency locked to TBC.
state of the RATEN input. Operating rates are shown
in Table 2.
to recover the serial clock from the received data
stream. The S2070 searches the serial bit stream for
the occurrence of a positive polarity COMMA sync
pattern (0011111xxx positive running disparity) to
perform word synchronization. Once synchronization
on both bit and word boundaries is achieved, the
receiver provides the decoded data on its parallel
stream. A simple state machine in the clock recovery
macro decides whether to acquire lock from the se-
rial data input or from the reference clock. The deci-
sion is based upon the frequency and run length of
the input serial data.
the S2070 will respond to variations in the serial data
input frequency (as compared to the reference fre-
quency). The new lock state is dependent upon the
current lock state, as shown in Table 3. The run-
length criteria ensure that the S2070 will respond ap-
length checker flags a condition of consecutive ones
or zeros across 12 parallel words. Thus, 119 or less
consecutive ones or zeros does not cause signal loss,
129 or more causes signal loss, and 120 128 may
or may not, depending on how the data aligns across
byte boundaries. If both the off-frequency detect test
and the run-length test is satisfied, the CRU will at-
tempt to lock to the incoming data.
data and the reference clock, the RBC0 and RBC1
remain phase continuous and glitch free, assuring
the integrity of downstream clocking.
jitter clock source. The frequency of the received
data stream must be within 200 ppm of the reference
clock to ensure reliable locking of the receiver PLL.
A single reference clock is provided to both the
transmit and receive PLLs.
allel output data, determined by the state of
EN_CDET. With EN_CDET held ACTIVE, the S2070
will detect and align to the 8B/10B COMMA
codeword anywhere in the data stream. When
EN_CDET is INACTIVE, no attempt is made to syn-
chronize on any particular incoming character.
Upon change of state of the EN_CDET input, the
COM_DET output response will be delayed by a
maximum of 3 byte times.
EN_CDET is active and the COMMA control charac-
ter is present on the RX[0:9] parallel data outputs.
The COM_DET output signal will be INACTIVE at all
puts, selected via the RATEN input. Table 4 shows
the operating rate scenarios. When RATEN is INAC-
TIVE, a data clock is provided on RBC1 at the data
rate. Data should be clocked on the rising edge of
RBC1. When RATEN is ACTIVE the device is in full
rate mode, and complementary TTL clocks are pro-
vided on the RBC0 and RBC1 outputs at 1/2 the
data rate as required by the Fibre Channel standard.
Data is clocked on the rising edges of both RBC0
and RBC1. See Figures 9 and 10.
quire that the COMMA sync character appears on
the rising edge of the RBC1 signal. In full rate mode
the phase of the data is adjusted such that this re-
quirement is met. No alignment is necessary when
the S2070 is operating in half rate mode (RATEN
INACTIVE) since the output clock frequency is equal
to the parallel word rate.
is illegal for multiple consecutive COMMA characters
to be generated. However, multiple consecutive
COMMA characters can occur in serial backplane
applications. The S2070 is able to operate properly
when multiple consecutive COMMA characters are
received: after the first COMMA is detected and
aligned, the RBC0/RBC1 clock operates without
glitches or loss of cycles. Additionally, COM_DET
stays high while multiple COMMAs are being output.
which the serial data from the transmitter replaces
external serial data. The loopback function is en-
abled when the loopback enable signal, EWRAP, is
system diagnostics and to perform off-line testing of
the interface to guarantee the integrity of the serial
channel before enabling the transmission medium.
Figure 3 shows the basic loopback operation.