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Datasheet: S2062 (Applied Micro Circuits Corp.)

Dual Serial Backplane Device

 

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1
S2062
DUAL SERIAL BACKPLANE DEVICE
June 20, 2000 / Revision B
S2062
DUAL SERIAL BACKPLANE DEVICE
DEVICE
SPECIFICATION
Figure 1. Typical Dual Gigabit Ethernet Application
FEATURES
Broad operating rate range (0.77 - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
Dual Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
Dual Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
On-chip 8B/10B line encoding and decoding for
two separate parallel 8-bit channels
2x8 Bit parallel TTL interface
Low-jitter serial PECL interface
Local Loopback
Interfaces with coax, twinax, or fiber optics
Single +3.3V supply, 1.37 W power dissipation
Compact 21mm x 21mm 156 TBGA package
APPLICATIONS
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2062 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides two
separate transceivers which can be operated indi-
vidually for a data capacity of >2 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip dual
receive PLL is used for clock recovery and data re-
timing on the two independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a 3.3V power supply and dissi-
pates 1.37 watts.
Figure 1 shows the S2062 and S2068 in a Gigabit
Ethernet application. Figure 2 combines the
S2062 with a crosspoint switch to demonstrate a
serial backplane application. Figure 3 is the input/
output diagram. Figures 4 and 5 show the transmit
and receive block diagrams, respectively.
MAC
(ASIC)
S2062
DUAL
GIGABIT
ETHERNET
INTERFACE
MAC
TO SERIAL BACKPLANE
S2068
GE INTERFACE
SERIAL BP DRIVER
(ASIC)
2
DUAL SERIAL BACKPLANE DEVICE
S2062
June 20, 2000 / Revision B
Figure 2. Typical Backplane Application
MAC
(ASIC)
S2062
ATM
Fibre
Channel
Ethernet
Etc.
MAC
(ASIC)
Crosspoint
Switch
S2016
S2025
MAC
(ASIC)
S2062
ATM
Fibre
Channel
Ethernet
Etc.
MAC
(ASIC)
MAC
(ASIC)
S2062
ATM
Fibre
Channel
Ethernet
Etc.
MAC
(ASIC)
MAC
(ASIC)
S2062
ATM
Fibre
Channel
Ethernet
Etc.
MAC
(ASIC)
BACKPLANE SIGNAL GROUP
3
S2062
DUAL SERIAL BACKPLANE DEVICE
June 20, 2000 / Revision B
Figure 3. S2062 Input/Output Diagram
REFCLK
RATE
RESET
TCLKO
TXAP/N
TXBP/N
RXBP/N
RXAP/N
DINA[0:7]
SOFA, KGENA
10
DINB[0:7]
SOFB, KGENB
10
TCLKA
TCLKB
10
RCA P/N
10
RCB P/N
DOUTA[0:7]
EOFA, KFLAGA
DOUTB[0:7]
EOFB, KFLAGB
CLKSEL
ERRA
ERRB
LPEN
CMODE
TMODE
TESTMODE1
TESTMODE
4
DUAL SERIAL BACKPLANE DEVICE
S2062
June 20, 2000 / Revision B
Figure 4. Transmitter Block Diagram
8B/10B
Encode
8
10
SOFA
KGENA
DINA[0:7]
8
Shift
Reg
8B/10B
Encode
8
10
SOFB
KGENB
DINB[0:7]
8
Shift
Reg
DIN PLL
10x/20x
REFCLK
CLKSEL
MUX
RATE
REFCLK
TCLKO
FIFO
(input)
FIFO
(input)
TXAP
TXAN
TXABP
TXBP
TXBN
TXBBP
TCLKB
TCLKA
0
1
0
1
TMODE
5
S2062
DUAL SERIAL BACKPLANE DEVICE
June 20, 2000 / Revision B
Figure 5. Receiver Block Diagram
DOUT CRU
Serial-
Parallel
EOFA
KFLAGA
ERRA
DOUTA[0:7]
RXAP
RXAN
Q
FIFO
(output)
LPEN
DOUT CRU
Serial-
Parallel
EOFB
KFLAGB
ERRB
DOUTB[0:7]
RXBP
RXBN
TXBBP
TXABP
REFCLK
8B/10B
Decode
8B/10B
Decode
8
8
RCAP/N
2
RCBP/N
2
CMODE
RATE
FIFO
(output)
8
8
10
10
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