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Datasheet: S2060 (Applied Micro Circuits Corp.)

Gigabit Ethernet Transceiver

 

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1
S2060
GIGABIT ETHERNET TRANSCEIVER
June 22, 2000 / Revision G
S2060
DEVICE
SPECIFICATION
GIGABIT ETHERNET TRANSCEIVER
FEATURES
Operating rate
1250 MHz (Gigabit Ethernet) line rates
Half and full VCO output rates
Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
Receiver PLL provides clock and data recovery
10-bit parallel TTL compatible interface
Low-jitter serial LVPECL compatible interface
Local loopback
Single +3.3 V supply, 620 mW power dissipation
64 PQFP or TQFP package
Continuous downstream clocking from receiver
Drives 30 m of Twinax cable directly
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
S2060
Gigabit
Ethernet
Controller
Optical
Tx
Optical
Rx
Optical
Tx
Optical
Rx
S2060
Gigabit
Ethernet
Controller
2
S2060
GIGABIT ETHERNET TRANSCEIVER
June 22, 2000 / Revision G
S2060 OVERVIEW
The S2060 transmitter and receiver provide serial-
ization and deserialization functions for block en-
coded data to implement a Gigabit Ethernet
interface. The S2060 functional block diagram is de-
picted in Figure 2. The sequence of operations is as
follows:
Transmitter
1.10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data input to the S2060 should be
from a DC-balanced encoding scheme, such as the
8B/10B transmission code, in which information to be
transmitted is encoded 8 bits at a time into 10-bit trans-
mission characters
1
. For reference, Table 1 shows the
mapping of the parallel data to the 8B/10B codes.
Loop Back
Local loopback provides a capability for performing
off-line testing. This is useful for ensuring the integ-
rity of the serial channel before enabling the trans-
mission medium. It also allows for system
diagnostics.
Figure 2. Functional Block Diagram
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Table 1. Data Mapping to 8B/10B
Alphabetic Representation
1. A.X. Widmer and P.A. Franaszek, "A Byte Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC 9391, May 1982.
FIFO
(4 x 10)
Shift
Register
10
10
PLL Clock
Recovery w/
lock detect
Shift
Register
D
Control
Logic
COMMA
Detect
Logic
D
Q
10
TX[0:9]
TBC
RXP
RXN
EWRAP
-LCK_REF
EN_CDET
RBC0
RBC1
COM_DET
RX[0:9]
TXN
TXP
S2060
RATEN
2:1
PLL Clock
Multiplier w/
lock detect
F0 = F1 x 10
3
S2060
GIGABIT ETHERNET TRANSCEIVER
June 22, 2000 / Revision G
TRANSMITTER DESCRIPTION
The S2060 transmitter accepts 10-bit parallel input
data and serializes it for transmission over fiber optic
or coaxial cable media. The chip is fully compatible
with the IEEE 802.3z Gigabit Ethernet standard, and
supports the Gigabit Ethernet data rate of 1250.0
Mbps. The S2060 uses a PLL to generate the serial
rate transmit clock. The transmitter runs at 10 times
the TBC input clock, and operates in either full rate
or half rate mode. At the full VCO rate the transmitter
runs at 1.25 GHz, while in half rate mode it operates
at 625 MHz.
Parallel-to-Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the trans-
mitter on the positive going edge of TBC. The data is
then clocked into the serial output shift register. The
shift register is clocked by the internally generated
bit clock which is 10x the TBC input frequency. TX[0]
is transmitted first.
Transmit Byte Clock (TBC)
The Transmit Byte Clock input (TBC) must be sup-
plied from a clock source with 100 ppm tolerance to
assure that the transmitted data meets the Gigabit
Ethernet frequency limits. The internal serial clock is
frequency locked to TBC (125.00 MHz).
TBC may be 62.5 MHz or 125 MHz, determined by
the state of the RATEN input. Operating rates are
shown in Table 2.
Transmit Latency
The average transmit latency is 4 byte times.
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Table 2. Operating Rates
4
S2060
GIGABIT ETHERNET TRANSCEIVER
June 22, 2000 / Revision G
RECEIVER DESCRIPTION
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. The S2060 searches the serial bit stream for
the occurrence of a positive polarity COMMA sync
pattern (0011111xxx positive running disparity) to
perform word synchronization. Once synchronization
on both bit and word boundaries is achieved, the
receiver provides the decoded data on its parallel
outputs.
Clock Recovery Function
Clock recovery is performed on the input data
stream. A simple state machine in the clock recovery
macro decides whether to acquire lock from the se-
rial data input or from the reference clock. The deci-
sion is based upon the frequency and run length of
the input serial data.
The lock to reference frequency criteria ensure that
the S2060 will respond to variations in the serial data
input frequency (as compared to the reference fre-
quency). The new lock state is dependent upon the
current lock state, as shown in Table 3. The run-
length criteria ensure that the S2060 will respond ap-
propriately and quickly to a loss of signal. The run-
length checker flags a condition of consecutive ones
or zeros across 12 parallel words. Thus, 119 or less
consecutive ones or zeros does not cause signal loss,
129 or more causes signal loss, and 120 128 may
or may not, depending on how the data aligns across
byte boundaries. If both the off-frequency detect test
and the run-length test is satisfied, the CRU will at-
tempt to lock to the incoming data.
In any transfer of PLL control between the serial
data and the reference clock, the RBC0 and RBC1
remain phase continuous and glitch free, assuring
the integrity of downstream clocking.
Reference Clock Input
The reference clock must be provided from a low
jitter clock source. The frequency of the received
data stream must be within 400 ppm of the reference
clock to ensure reliable locking of the receiver PLL.
A single reference clock is provided to both the
transmit and receive PLL's.
Data Output
The S2060 provides either framed or unframed par-
allel output data, determined by the state of
EN_CDET. With EN_CDET held ACTIVE, the S2060
will detect and align to the 8B/10B COMMA
codeword anywhere in the data stream. When
EN_CDET is INACTIVE, no attempt is made to syn-
chronize on any particular incoming character. The
S2060 will achieve bit synchronization within 250 bit
times and begin to deliver unframed parallel output
data words whenever it has received full transmis-
sion words. Upon change of state of the EN_CDET
input, the COM_DET output response will be de-
layed by a maximum of 3 byte times.
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Table 3. Lock to Reference Frequency Criteria
5
S2060
GIGABIT ETHERNET TRANSCEIVER
June 22, 2000 / Revision G
The COM_DET output signal is ACTIVE whenever
EN_CDET is active and the COMMA control charac-
ter is present on the RX[0:9] parallel data outputs.
The COM_DET output signal will be INACTIVE at all
other times.
Parallel Output Clock Rate and Data Stretching
The S2060 supports both full rate and half rate out-
puts, selected via the RATEN input. Table 4 shows
the operating rate scenarios. When RATEN is INAC-
TIVE, a data clock is provided on RBC1 at the data
rate. Data should be clocked on the rising edge of
RBC1. When RATEN is ACTIVE the device is in full
rate mode, and complementary TTL clocks are pro-
vided on the RBC0 and RBC1 outputs at 1/2 the
data rate as required by the Gigabit Ethernet Stan-
dard. Data is clocked on the rising edges of both
RBC0 and RBC1. See Figures 11 and 12.
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Table 4. Operating Rates
Fibre Channel and Gigabit Ethernet Standards re-
quire that the COMMA sync character appears on
the rising edge of the RBC1 signal. In full rate mode
the phase of the data is adjusted such that this re-
quirement is met. No alignment is necessary when
the S2060 is operating in half rate mode since the
output clock frequency is equal to the parallel word
rate (RATEN INACTIVE).
In ethernet applications it is illegal for multiple con-
secutive COMMA characters to be generated. How-
ever, multiple consecutive COMMA characters can
occur in serial backplane applications. The S2060 is
able to operate properly when multiple consecutive
COMMA characters are received: after the first
COMMA is detected and aligned, the RBC0/RBC1
clock operates without glitches or loss of cycles.
Additionally, COM_DET stays high while multiple
COMMAS are being output.
Receive Latency
The average receive latency is 8 byte times.
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