standards and IEEE 802.3z Gigabit Ethernet
differential LVPECL or LVTTL reference
· 10-bit parallel LVTTL compatible interface
· 1.1mW typical power dissipation
· +3.3V power supply
· Low-jitter serial LVPECL compatible interface
· Lock detect
· Dual serial inputs and outputs
· Local loopback
· Compact 10mm x 10mm 64 PQFP package
· Fibre Channel framing performed by receiver
· Continuous downstream clocking from receiver
· Low jitter LVPECL reference clock input option
· Frame buffer
· Switched networks
· Data broadcast environments
· Proprietary extended backplanes
· RAID drives
· Mass storage devices
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces conforming to
the requirements of the ANSI X3T11 Fibre Channel
specification and IEEE 802.3z Gigabit Ethernet. The
chip runs at 1250.0, and 1062.5 Mbit/s data rates
with associated 10-bit data word.
vides dual transmit and receive serial I/O in addition
to an optional LVTTL or differential LVPECL refer-
ence clock input and high drive LVTTL outputs. The
dual transmit and receive serial I/O are useful for
backbone applications in which redundant optical or
electrical links are required. The differential LVPECL
reference clock provides the lowest transmitter output
jitter solution. The high drive LVTTL outputs allow
longer trace lengths or connectors to be used be-
tween the S2054 and the Media Access Controller.
lel conversion and framing for block-encoded data. The
transmitter's on-chip PLL synthesizes the high-speed
clock from a low-speed reference. The receiver's on-
chip PLL synchronizes directly to incoming digital signal
to receive the data stream. The transmitter and re-
ceiver each support differential LVPECL-compatible I/
O for fiber optic component interfaces, to minimize
crosstalk and maximize data integrity. Local line
loopback mode is provided for system diagnostics. Dual
serial inputs and dual serial outputs facilitate redun-
dant design and provide maximum flexibility.
the chip, which is compatible with AMCC's S2036 Open
Fiber Control (OFC) device (for 1062 operation only).
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2054 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
2. Parallel-to-serial conversion
3. Serial output
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters
serializes it for transmission over fiber optic or coaxial
cable media. The chip is fully compatible with the ANSI
X3T11 Fibre Channel standard, and supports the Fi-
bre Channel and Gigabit Ethernet data rates of 1250
and 1062 Mbit/sec. (See Figure 3.)
LVTTL. Data is clocked into the S2054 on the rising
edge of REFCLK.
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmitter
using the reference clock. The data is then clocked
into the serial output shift register. The shift register
is clocked by the internally generated bit clock which
is 10x the reference clock input frequency. D0 is trans-
mitted first as described in annex N and Tables 22
and 23 of FC-PH. Table 1 shows the mapping of the
parallel data to the 8B/10B codes. Two serial data
outputs are provided.
ther a differential LVPECL (REFCLKP/N) or
single-ended LVTTL (TREFCLK) clock source with
100 PPM tolerance to assure that the transmitted data
meets the Fibre Channel frequency limits. The inter-
nal serial clock is frequency locked to the reference
clock (125.00 or 106.25 MHz).
X3T11 Fibre Channel specification and the IEEE 802.3z
Gigabit Ethernet receiver functions. A block diagram
showing the basic chip function is provided in Figure 3.
RCVSEL pin is used to select the active input. When-
ever a signal is present on the selected pin, the S2054
attempts to achieve synchronization on both bit and
transmission-word boundaries of the received encoded
bit stream. Received data from the incoming bit stream
is provided on the device's parallel data outputs.
optic or coaxial cable interface. The serial input stream is
the result of the serialization of 8B/10B encoded data by
an FC compatible transmitter. Clock recovery is performed
on-chip, with the output data presented to the Fibre
Channel transmission layer as 10-bit parallel data.
PLL clock recovery circuit will lock to the data stream
if the clock to be recovered is within
is used to retime the input data stream. The data is
then clocked into the serial to parallel output registers
on the edge of RBC1. Data is clocked out on the
rising edge of RBC1 and RBC0. The parallel data out
is 10 bits wide. The word clock (RBC1) is synchro-
nized to the incoming data stream word boundary by
the detection of the Fibre Channel comma character
(0011111XXX, positive running disparity).
and data word alignment of the LVTTL compatible out-
put data bus. In systems where the COM_DET function
is undesired, a LOW on the EN_CDET input disables
the COM_DET function and the data will be "un-framed".
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words whenever
it has received full transmission words. No attempt is made
to synchronize on any particular incoming character.
K28.5 character (positive disparity) is present on the
parallel data outputs and EN_CDET is High. If
EN_CDET is Low, comma characters will not be re-
ported. The COM_DET output signal will be low at all
the receiver phase-locked loop (PLL) clock recovery
unit. The PLL will lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a se-
rial switch, for example) the PLL will not indicate an
out-of-lock state, but will recover the correct phase align-
ment within 50 to 250 bit times, depending on the input
eye opening. (See Fig. 13). If a run length of 80-160
bits is exceeded, or if the input data rate varies by
more than approximately 600 ppm compared to the
reference clock, the loop will be declared out of lock.
When lock is lost, the PLL will shift from the serial input
data to the reference clock, so that the downstream
clock will maintain the correct frequency.
reference clock, the RBC1/RBC0 output remains phase
continuous and glitch free, assuring the integrity of down-
holding the LCK_REF signal Low. For normal opera-
tion, LCK_REF can be left unconnected or held High.
transmitter is internally routed to the receiver, where
the clock is extracted and the data is deserialized.
The parallel data is then sent to the subsystem for
verification. The high speed serial outputs are dis-
abled during loopback. This loopback mode provides
the capability to perform offline testing of the inter-
face to guarantee the integrity of the serial channel
before enabling the transmission medium. It also al-
lows system diagnostics.
1062 Mbit/s. Operation at other rates is possible if the
rate falls between the nominal rates. REFCLK must
be selected to be within 100 ppm of the desired byte
or word clock rate.