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Datasheet: S2054 (Applied Micro Circuits Corp.)

Bicmos Lvpecl Clock Generator Fibre Channel and Gigabit Ethernet Transceiver

 

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1
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER S2054
BiCMOS LVPECL CLOCK GENERATOR
®
DEVICE
SPECIFICATION
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER S2054
FEATURES
· Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards and IEEE 802.3z Gigabit Ethernet
Applications
· Transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
differential LVPECL or LVTTL reference
· Receiver PLL configured for clock and data
recovery
· 1250 and 1062 Mb/s operation
· 10-bit parallel LVTTL compatible interface
· 1.1mW typical power dissipation
· +3.3V power supply
· Low-jitter serial LVPECL compatible interface
· Lock detect
· Dual serial inputs and outputs
· Local loopback
· Compact 10mm x 10mm 64 PQFP package
· Fibre Channel framing performed by receiver
· Continuous downstream clocking from receiver
· Low jitter LVPECL reference clock input option
APPLICATIONS
High-speed data communications
· Workstation
· Frame buffer
· Switched networks
· Data broadcast environments
· Proprietary extended backplanes
· RAID drives
· Mass storage devices
GENERAL DESCRIPTION
The S2054 transmitter and receiver chip is designed
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces conforming to
the requirements of the ANSI X3T11 Fibre Channel
specification and IEEE 802.3z Gigabit Ethernet. The
chip runs at 1250.0, and 1062.5 Mbit/s data rates
with associated 10-bit data word.
The S2054 is similar to the S2052. The S2054 pro-
vides dual transmit and receive serial I/O in addition
to an optional LVTTL or differential LVPECL refer-
ence clock input and high drive LVTTL outputs. The
dual transmit and receive serial I/O are useful for
backbone applications in which redundant optical or
electrical links are required. The differential LVPECL
reference clock provides the lowest transmitter output
jitter solution. The high drive LVTTL outputs allow
longer trace lengths or connectors to be used be-
tween the S2054 and the Media Access Controller.
The chip performs parallel-to-serial and serial-to-paral-
lel conversion and framing for block-encoded data. The
transmitter's on-chip PLL synthesizes the high-speed
clock from a low-speed reference. The receiver's on-
chip PLL synchronizes directly to incoming digital signal
to receive the data stream. The transmitter and re-
ceiver each support differential LVPECL-compatible I/
O for fiber optic component interfaces, to minimize
crosstalk and maximize data integrity. Local line
loopback mode is provided for system diagnostics. Dual
serial inputs and dual serial outputs facilitate redun-
dant design and provide maximum flexibility.
Figure 1 shows a typical configuration incorporating
the chip, which is compatible with AMCC's S2036 Open
Fiber Control (OFC) device (for 1062 operation only).
Figure 1. System Block Diagram
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2036
Open Fiber
Control
(OFC)
S2036
Open Fiber
Control
(OFC)
S2054 S2054
Gigabit
Ethernet
Controller
Gigabit
Ethernet
Controller
2
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
Loopback
Local loopback is supported by the chip, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S2054 OVERVIEW
The S2054 transmitter and receiver provide serializa-
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2054 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
Transmitter
1. 10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data handled by the S2054 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters
1
, and be compliant with
ANSI X3.230 FC-PH (Fibre Channel Physical and Sig-
naling Interface).
1. A.X. Widmer and P.A. Franaszek, "A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code," IBM Research Report RC 9391,
May 1982.
Figure 2. Interface Diagram
Parallel
Data In
S2054
Transceiver
REFCLK
Serial
Data In
RCVSEL
RBC0/1
Parallel
Data Out
COM_DET
Serial
Data Out
0
1
0
1
TESTEN
TX [0:9]
10
10
PLL CLOCK
MULTIPLIER
F0 = F1 X 10
SHIFT
REGISTER
TX0P/N
EWRAP
TX1P/N
D
Q
PLL CLOCK
RECOVERY
3:1
D
10
2
2
2
2
D
BITCLK
Q
COM_DET
DETECT
LOGIC
CONTROL
LOGIC
RX0P/N
REFCLKP/N
TREFCLK
RX1P/N
TP/N
EWRAP
RCVSEL
-LCK_REF
EN_CDET
RX[0:9]
RBC1
COM_DET
RBC0
SHIFT
REGISTER
Input
Latch
Figure 3. Functional Block Diagram
3
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
REFCLKP/N
TREFCLK
(Input)
RBC0
(Output)
COM_DET
(Output)
PARALLEL
DATA BUS
(Input)
PARALLEL
DATA BUS
(Output)
SERIAL DATA
K28.5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
K28.5
K28.5
K28.5
K28.5
K28.5
RBC1
(Output)
INPUT TIMING
OUTPUT TIMING
Figure 4. Functional Waveform (1250 and 1062.5 Mbit/sec)
TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2054 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The chip is fully compatible with the ANSI
X3T11 Fibre Channel standard, and supports the Fi-
bre Channel and Gigabit Ethernet data rates of 1250
and 1062 Mbit/sec. (See Figure 3.)
Data Input
Transmit data is provided to the S2054 as 10-bit wide
LVTTL. Data is clocked into the S2054 on the rising
edge of REFCLK.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmitter
using the reference clock. The data is then clocked
synchronous to the clock synthesis unit serial clock
into the serial output shift register. The shift register
is clocked by the internally generated bit clock which
is 10x the reference clock input frequency. D0 is trans-
mitted first as described in annex N and Tables 22
and 23 of FC-PH. Table 1 shows the mapping of the
parallel data to the 8B/10B codes. Two serial data
outputs are provided.
Reference Clock Input
The reference clock input must be supplied with ei-
ther a differential LVPECL (REFCLKP/N) or
single-ended LVTTL (TREFCLK) clock source with
100 PPM tolerance to assure that the transmitted data
meets the Fibre Channel frequency limits. The inter-
nal serial clock is frequency locked to the reference
clock (125.00 or 106.25 MHz).
Data Byte
9
8
7
6
5
4
3
2
1
0
TX[0:9] or
RX[0:9]
8b/10b alphabetic
representation
j
h
g
f
i
e
d
c
b
a
Table 1. Data Mapping to 8b/10b Alphabetic Representation
4
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
RECEIVER FUNCTIONAL DESCRIPTION
The S2054 receiver is designed to implement the ANSI
X3T11 Fibre Channel specification and the IEEE 802.3z
Gigabit Ethernet receiver functions. A block diagram
showing the basic chip function is provided in Figure 3.
Two serial inputs are provided by the S2054. The
RCVSEL pin is used to select the active input. When-
ever a signal is present on the selected pin, the S2054
attempts to achieve synchronization on both bit and
transmission-word boundaries of the received encoded
bit stream. Received data from the incoming bit stream
is provided on the device's parallel data outputs.
The S2054 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream is
the result of the serialization of 8B/10B encoded data by
an FC compatible transmitter. Clock recovery is performed
on-chip, with the output data presented to the Fibre
Channel transmission layer as 10-bit parallel data.
Serial/Parallel Conversion
Serial data is received on the RX[0:1]P/N pins. The
PLL clock recovery circuit will lock to the data stream
if the clock to be recovered is within
±
100 PPM of the
internally generated bit rate clock. The recovered clock
is used to retime the input data stream. The data is
then clocked into the serial to parallel output registers
on the edge of RBC1. Data is clocked out on the
rising edge of RBC1 and RBC0. The parallel data out
is 10 bits wide. The word clock (RBC1) is synchro-
nized to the incoming data stream word boundary by
the detection of the Fibre Channel comma character
(0011111XXX, positive running disparity).
Framing
The S2054 provides COM_DET character recognition
and data word alignment of the LVTTL compatible out-
put data bus. In systems where the COM_DET function
is undesired, a LOW on the EN_CDET input disables
the COM_DET function and the data will be "un-framed".
When framing is disabled by low EN_CDET, the S2054
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words whenever
it has received full transmission words. No attempt is made
to synchronize on any particular incoming character.
The COM_DET output signal will go high whenever a
K28.5 character (positive disparity) is present on the
parallel data outputs and EN_CDET is High. If
EN_CDET is Low, comma characters will not be re-
ported. The COM_DET output signal will be low at all
other times.
Lock Detect
The S2054 lock detect function monitors the state of
the receiver phase-locked loop (PLL) clock recovery
unit. The PLL will lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a se-
rial switch, for example) the PLL will not indicate an
out-of-lock state, but will recover the correct phase align-
ment within 50 to 250 bit times, depending on the input
eye opening. (See Fig. 13). If a run length of 80-160
bits is exceeded, or if the input data rate varies by
more than approximately 600 ppm compared to the
reference clock, the loop will be declared out of lock.
When lock is lost, the PLL will shift from the serial input
data to the reference clock, so that the downstream
clock will maintain the correct frequency.
In any transfer of PLL control from the serial data to the
reference clock, the RBC1/RBC0 output remains phase
continuous and glitch free, assuring the integrity of down-
stream clocking.
Lock to Reference
The S2054 can be forced to lock to the REFCLK by
holding the ­LCK_REF signal Low. For normal opera-
tion, ­LCK_REF can be left unconnected or held High.
OTHER OPERATING MODES
Loopback
When local loopback is enabled, serial data from the
transmitter is internally routed to the receiver, where
the clock is extracted and the data is deserialized.
The parallel data is then sent to the subsystem for
verification. The high speed serial outputs are dis-
abled during loopback. This loopback mode provides
the capability to perform offline testing of the inter-
face to guarantee the integrity of the serial channel
before enabling the transmission medium. It also al-
lows system diagnostics.
Operating Frequency Range
The S2054 is optimized for operation at 1250 and
1062 Mbit/s. Operation at other rates is possible if the
rate falls between the nominal rates. REFCLK must
be selected to be within 100 ppm of the desired byte
or word clock rate.
5
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
Table 2. S2054 Transmitter Pin Assignment and Descriptions
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