· 10-bit or 20-bit parallel TTL compatible
· +3.3/+5 V power supply
· Low-jitter serial PECL compatible interface
· Lock detect
· Local loopback
· Compact 52 pin PQFP package
· Fibre Channel framing performed by receiver
· Continuous downstream clocking from receiver
· TTL compatible outputs possible with +5V I/O
· Ethernet backbone connections
· Frame buffer
· Switched networks
· Data broadcast environments
· Proprietary extended backplanes
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the IEEE 802.3z
specification. The chipset is Gigabit Ethernet compli-
ant and supports 1250 Mb/s with an associated 10 or
20-bit data word.
parallel conversion and framing for block-encoded
data. The S2046 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2047
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3 V or a +5 V power
supply. With a 3.3 V power supply the chipset dissi-
pates only 1 W typically.
porating the chipset.
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
serialization and deserialization functions for block-
encoded data to implement a Gigabit interface.
Operation of the S2046/S2047 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
2. Parallel-to-serial conversion
3. Serial output
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
S2047 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission
ent to the user. Details of data timing can be seen in
indicates that the PLL is locked (synchronized) to the
serializes it for transmission over fiber optic or coaxial
cable media. The S2046 is fully compliant with the
IEEE 802.3z Specification, and supports the Gigabit
Ethernet data rate of 1250 Mbit/sec.
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
20-bit wide data from the input latch and converts it
to a serial data stream. Parallel data is latched into
the transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
generated bit clock which is 10 or 20 times the
REFCLK input frequency. The state of the serial out-
puts is controlled by the output enable pins, OE0 and
OE1. D is transmitted first in 10-bit mode. D is
transmitted first in 20-bit mode. Table 2 shows the
mapping of the parallel data to the 8B/10B codes.
lel data inputs. Word width is selectable via the DWS
pin. In 10-bit mode, D[10:19] are used and D[0:9] are
plied with a PECL single-ended AC coupled crystal
clock source with 100 PPM tolerance to assure that
the transmitted data meets the Fibre Channel
and IEEE 802.3z Specification frequency limits. The
internal serial clock is frequency locked to the
reference clock. Refer to Table 1 for reference clock
IEEE 802.3z Specification receiver functions. A block
diagram showing the basic chip function is provided
in Figure 4.
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device's parallel data outputs.
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by a compatible transmitter. Clock recovery is
performed on-chip, with the output data presented to
the transmission layer as 10-bit or 20-bit parallel data.
The chip operates at the Gigabit Ethernet frequency
of 1250 Mbit/s.
clock recovery circuit will lock to the data stream if
the clock to be recovered is within
is used to retime the input data stream. The data is
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLKN) is synchronized to the incoming
data stream word boundary by the detection of the
K28.5 synchronization pattern (0011111010, positive
parallel data outputs. This option is selectable via
the DWS pin. See Table 3. In 10-bit mode, the 10-bit
data word is output on both D[10:19] and D[0:9]
single-ended AC coupled crystal clock source at
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLKN phase will be adjusted. No glitches will
occur in the RCLKN signal due to the realignment. In
systems where the SYNC detect function is undes-
ired, a LOW on the SYNCEN input disables the SYNC
function and the data will be "un-framed."
simply achieves bit synchronization and begins to de-
liver parallel output data words whenever it has
received full transmission words. No attempt is made
to synchronize on any particular incoming character.
character (positive disparity) is present on the parallel
data outputs. The SYNC output signal will be low at
all other times. This is true whether the S2047 is
operating in 10-bit mode or in 20-bit mode.
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock after the start of receiving serial
data inputs. If the serial data inputs have an instanta-
neous phase jump (from a serial switch, for example)
the PLL will not indicate an out-of-lock state, but will
recover the correct phase alignment within 250 bit
times. If a run length of 64 bits is exceeded, or if the
transition density is less than 12%, the loop will be
declared out of lock and will attempt to re-acquire bit
synchronization. When lock is lost, the PLL will shift
from the serial input data to the reference clock, so
that correct frequency downstream clocking will be
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
cedure to correctly achieve lock on the serial data
inputs. At power-up or loss of lock, the PLL must first
acquire frequency lock to the local reference clock.
This can be accomplished connecting the LOCK_REF
pin to a 10 ms reset signal. If this is not possible, the
PLL can also be initialized by guaranteeing that no
data is seen at the serial data inputs for a minimum
of 10 ms upon power-up. If the serial data inputs
cannot be controlled, then the S2047 can be put into
the loopback mode and the loopback outputs of the
S2046 must be quiescent for a minimum of 10 ms