· 1 watt typical power dissipation for chipset
· +3.3/+5V power supply
· Low-jitter serial PECL compatible interface
· Lock detect
· Local loopback
· Compact 52 PQFP package
· Fibre Channel framing performed by receiver
· Continuous downstream clocking from receiver
· TTL compatible outputs possible with +5V I/O
· Switched networks
· Proprietary extended backplanes
· Mass storage devices/RAID drives
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is Gigabaud
Link Module (GLM) compliant and supports 1062 Mb/s
(GLM) and 531 Mb/s Half-GLM (HGLM) and 266 Mb/s
Quarter-GLM (QGLM) modes with associated 10 or
20-bit data word.
parallel conversion and framing for block-encoded
data. The S2044 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2045
on-chip PLL synchronizes directly to incoming digital
signals, to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Local
loopback allows for system diagnostics. The I/O sec-
tion can operate from either a +3.3V or a +5V power
supply. With a 3.3V power supply the chipset dissi-
pates only 1W typically.
porating the chipset. The chipset is compatible with
AMCC's S2036 Open Fiber Control (OFC) device.
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
serialization and deserialization functions for block-
encoded data to implement a Fibre Channel interface.
Operation of the S2044/S2045 chips is straightfor-
ward, as depicted in Figure 2. The sequence of
operations is as follows:
2. Parallel-to-serial conversion
3. Serial output
2. Serial-to-parallel conversion
3. Frame detection
4. 10/20-bit parallel output
S2045 devices should be from a DC-balanced en-
coding scheme, such as the 8B/10B transmission
code, in which information to be transmitted is en-
coded 8 bits at a time into 10-bit transmission characters
the user. Details of data timing can be seen in Figure 5.
indicates that the PLL is locked (synchronized) to the
and serializes it for transmission over fiber optic or
coaxial cable media. The chip is fully compatible with
the ANSI X3T11 Fibre Channel standard, and sup-
ports the Fibre Channel standard's data rates of 1062,
531 and 266 Mbit/sec.
20 bits wide, depending upon DWS pin selection. A
block diagram showing the basic chip function is
shown in Figure 3.
bit wide data from the input latch and converts it to a
serial data stream. Parallel data is latched into the
transmitter on the positive going edge of REFCLK.
The data is then clocked synchronous to the clock
synthesis unit serial clock into the serial output shift
register. The shift register is clocked by the internally
input frequency. The state of the serial outputs is
controlled by the output enable pins, OE0 and OE1.
D10 is transmitted first in 10-bit mode. D0 is transmit-
ted first in 20-bit mode. Table 2 shows the mapping
of the parallel data to the 8B/10B codes.
data inputs. Word width is selectable via the DWS pin. In
10-bit mode, D10D19 are used and D0-D9 are ignored.
plied with a PECL single-ended AC coupled crystal
clock source with 100 PPM tolerance to assure that
the transmitted data meets the Fibre Channel fre-
quency limits. The internal serial clock is frequency
locked to the reference clock. The word rate clock
(TCLK, TCLKN) output frequency is determined by
the selected operating speed and word width. Refer
to Table 1 for TCLK/TCLKN clock frequencies.
ANSI X3T11 Fibre Channel specification receiver func-
tions. A block diagram showing the basic chip function
is provided in Figure 5.
achieve synchronization on both bit and transmission-
word boundaries of the received encoded bit stream.
Received data from the incoming bit stream is pro-
vided on the device's parallel data outputs.
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by an FC compatible transmitter. Clock recovery
is performed on-chip, with the output data presented
to the Fibre Channel transmission layer as 10- or 20-
bit parallel data. The chip is programmable to operate
at the Fibre Channel specified operating frequencies
of 1062, 531 and 266 Mbit/s.
clock recovery circuit will lock to the data stream if
the clock to be recovered is within
is used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters. The parallel data out can be either 10 or 20 bits
wide determined by the state of the DWS pin. The
word clock (RCLK) is synchronized to the incoming
data stream word boundary by the detection of the
fiber channel K28.5 synchronization pattern
(0011111010, positive running disparity).
parallel data outputs. This option is selectable via the
DWS pin. See Tables 3 and 4. In 10-bit mode, D10
D19 are used and D0D9 are driven to the logic high state.
PECL single-ended AC coupled crystal clock source
data word alignment of the TTL level compatible out-
put data bus. During the data realignment process,
the RCLK phase will be adjusted. No glitches will
occur in the RCLK signal due to the realignment. In
systems where the SYNC detect function is undes-
ired, a LOW on the SYNCEN input disables the SYNC
function and the data will be "un-framed".
simply achieves bit synchronization within 250 bit times
and begins to deliver parallel output data words when-
ever it has received full transmission words. No
attempt is made to synchronize on any particular in-
character (positive disparity) is present on the parallel
data outputs. The SYNC output signal will be low at
all other times. This is true whether the S2045 is
operating in 10-bit mode or in 20-bit mode.
the phase-locked loop (PLL) clock recovery unit. The
PLL will indicate lock within 250 bit times after the
start of receiving serial data inputs. If the serial data
inputs have an instantaneous phase jump (from a
an out-of-lock state, but will recover the correct phase
alignment within 250 bit times. If a run length of 64
bits is exceeded, or if the transition density is less
than 12%, the loop will be declared out of lock and
will attempt to re-acquire bit synchronization. When
lock is lost, the PLL will shift from the serial input data
to the reference clock, so that correct frequency down-
stream clocking will be maintained.
the reference clock, the RCLK/RCLKN output remains
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
cedure to correctly achieve lock on the serial data
inputs. At power-up or loss of lock, the PLL must first
acquire frequency lock to the local reference clock.
This can be accomplished connecting the LOCK_REF
pin to a 10 ms reset signal. If this is not possible, the
PLL can also be initialized by guaranteeing that no
data is seen at the serial data inputs for a minimum
of 10 ms upon power-up. If the serial data inputs
cannot be controlled, then the S2045 can be put into
the loopback mode and the loopback outputs of the
S2044 must be quiescent for a minimum of 10 ms