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Datasheet: S2028 (Applied Micro Circuits Corp.)

33x32 1.25 Gb/s Differential Crosspoint Switch

 

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1
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Figure 1. Functional Block Diagram
FEATURES
33 x 32 differential crosspoint switch
Full broadcast switching capability
Differential 10K PECL data path
Configurable differential output driver
controls
Up to 1.25 Gbit/s NRZ data rate
TTL configuration controls
Reconfigurable without disturbing
operation
Single cycle broadcast configuration
High-speed multicast and fast unicast
configuration (100 MHz)
"Break" feature to disable previous
multicast configuration
224-pin LDCC package
APPLICATIONS
Internet Switches
Datacom or telecom switching
Digital demultiplexing
Microwave or fiber-optic data distribution
High-speed automatic test equipment
Digital video
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
DEVICE
SPECIFICATION
GENERAL DESCRIPTION
The S2028 is a very high-speed 33 x 32 differential
crosspoint switch with fast multicast and broadcast
capabilities. It consists of 32 differential PECL input
signal pairs that can be connected to any or all of its
32 differential PECL output signal pairs. In addition,
the differential output drivers can be individually con-
figured to gate in an additional broadcast channel.
This channel can be used as a default advertise
channel, or to supply a signal such as a clock to
simplify interface design.
Along with a single cycle reconfiguration of the entire
33 x 32 crosspoint switch, the S2028 features single
cycle broadcast and fast two cycle multicast configu-
ration. A "break" feature allows fast unicast or
multicast disable of the previous configuration.
The S2028 contains a unique memory map, which
provides full support of the broadcast, multicast, and
unicast modes.
The differential 10K PECL logic data path makes the
part ideal for high-speed applications. The differential
nature of the data path is retained throughout the
crosspoint structure, to minimize data distortion and to
handle NRZ data rates up to 1.25 gigabits per second.
PECL
Diff.
Input
Buffers
PECL
Diff.
Output
Buffers
33 x 32
Differential
Crosspoint
66
64
DIN00P
DIN31P
DOUT00P
DOUT31P
Active Configuration Latch
192
16
32 x 6
Configuration
Register File
192
RESETN
CONFIGN
CRFDATA
LOADN
CRFADDR
OADDR/OUTPUT MASK
DOUT00N
DOUT31N
DIN00N
DIN31N
ADVERTISEP
ADVERTISEN
1
BROADCAST
1
MULTICAST
1
BREAK
1
BANKSEL
5
IADDR
BROADCAST
MULTICAST
BREAK
BANKSEL
IADDR
1
ADVERT
ADVERT
10
1
WRITE
CSN
1
CHIP SELECT
2
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Figure 2. Data Transfer Waveforms
tCFDO
tLDDO
tDIDO
DIMPW
DIN [31:0] P/N
ADVERTISEP/N
DOUT [31:0] P/N
CONFIGN
LOADN
A
A
B
C
D
E
B
C
D
E
CSN
Data Transfer
For each configured connection between a differen-
tial input pair and an enabled output pair, any data
appearing at the input pair and switching at up to
1.25 Gb/s will be passed immediately through to the
output pair.
Configuration
The S2028 can be selectively reconfigured one out-
put channel at a time in unicast mode, 16 output
channels at a time in multicast mode, and all 32
output channels simultaneously in broadcast mode.
Any number of output channels can be reconfigured
simultaneously using the CONFIGN control. Con-
figuration data is stored in all 32 registers, one
register for each output channel. As shown in Figure
1, the configuration data is passed in parallel from
all 32 registers to a bank of latches which hold the
active switch configuration. This two-state arrange-
ment allows any number of output channels to be
reconfigured simultaneously.
Each output configuration register holds 6 bits. Five
bits are used to select which input channel will be
connected to the output channel, and one bit is used
to override the input address and instead channel
the ADVERTISEP/N input to that output.
The S2028A 33 X 32 Crosspoint Switch interface is
designed to connect directly to a microprocessor's
address and data bus and R/W signal. A CS input
(CSN) is provided to simplify interfacing to the
microprocessor's address bus. Most of the device's
functions can be programmed by a single instruction
in firmware. See the memory map in Figure 3. The
memory map depends on the hardware interface,
and can be mapped to any 1024 byte address range.
In general, the address bus will specify the
crosspoint switch input channel, and the data bus
will specify the crosspoint switch output channel.
The microprocessor or host hardware presents the
address and data to the S2028A, the decoder logic
enables CSN, and then the microprocessor strobes
the Read/Write* signal (LOADN). (See Figure 2.)
Broadcast Mode
Writing to any address in the Broadcast Address
Space (512-1023) will broadcast the input channel
specified on the address bus (IADDR) to all 32 out-
put channels. If the ADVERT bit is set to a 1, IADDR
is ignored and the ADVERTISE input is broadcast to
all 32 output channels. Broadcasting is a single cycle
operation, and does not require strobing of
CONFIGN.
TTL configuration controls simplify interfacing to
slower speed circuitry. Once a new configuration
has been entered into the configuration register file,
the S2028 can be completely reconfigured in only
10 ns without disturbing switch operations.
The configuration register can also be put into trans-
parent mode, reconfiguring all addressed outputs
within 10ns after the LOADN signal goes low.
3
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Multicast Mode
In Multicast Mode, a group of 16 output channels
can be configured to connect to one input channel in
a single cycle. There are two output channel groups,
so all 32 output channels can be configured in two
cycles. Each group has its own addess range. Group
0 configures output channels 0-15 while Group 1
configures output channels 16-31. Each bit of the 16
bit data bus (CRFDATA) specifies which of the 16
output channels in the group are to be configured to
connect to the input channel.
The address bus IADDR specifies the input channel,
and the ADVERT input specifies whether to override
that input channel with the ADVERTISEP/N input.
The BANKSEL bit specifies which of the two sets of
16 output channels is being addressed. For ex-
ample, if the address bus contains "0101011001"
and the data bus contains "01000110 10101100",
then output channels 18, 19, 21, 23, 25, 26 and 30
are configured for connection to input channel 25. If
the address bus contains "0101111001" and the data
bus is unchanged, then output channels 18, 19, 21,
23, 25, 26 and 30 are configured for connection to
the ADVERTISEP/N input.
The Multicast Address Range is from 256-511. Writ-
ing to address range 256-383 will maintain the prior
configuration for a particular channel, if that
channel's output mask bit is set to a "0". The ad-
dress range 384-511 activates the "break" feature of
the S2028A 33X32 Crosspoint Switch. In this mode,
for each output channel whose mask bit is set to 0, if
the prior configured input channel matches the new
requested input channel, the prior configuration is
broken and the ADVERTISE input is connected to
that output.
Unicast Mode
Writing to the Unicast Address Range (0-255) will
configure the input channel specified on the address
bus (IADDR) to connect to the output channel speci-
fied on the lower 5 bits of the data bus (OADDR).
However, if the ADVERT bit is set to a 1, IADDR is
ignored and the output channel OADDR is config-
ured to connect to the ADVERTISEP/N input.
Writing to Address Range 0-127 will maintain the
prior configuration for a particular channel, if that
channel's output mask bit is set to a "0". The ad-
dress range 128-255 activates the "break" feature. In
this mode, for each output channel whose mask bit
is set to 0, if the prior configured input channel
matches the new requested input channel, the prior
configuration is broken and the ADVERTISE input is
connected to that output.
Reconfiguration
When the differential switch is to be reconfigured,
the S2028A minimizes the time required through the
use of an active configuration latch. While the switch
is operational, and prior to the time at which it must
be reconfigured, a new configuration can be loaded
into the output pair configuration registers. Once the
32 output pair configuration registers contain the de-
sired connection and output pair driver control
information, the contents of the registers are trans-
ferred in parallel to the active configuration latch by
the CONFIGN strobe.This allows multiple connec-
tions to be simultaneously changed. Broadcast
mode is a single cycle operation and does not re-
quire strobing CONFIGN.
The configuration latch can be made transparent by
tying the CONFIGN input to a logic 0. When this is
done, changes strobed into the output pair configu-
ration registers by the LOADN input will be passed
immediately to the switch.
Reset Behavior
When the RESETN input is asserted, the S2028A
assumes a configuration where the ADVERTISEP/N
channel is broadcast to all of the differential output
drivers. Individual output drivers then remain in this
state after RESETN is deasserted, until they are ex-
plicitly reconfigured to a new input address.
4
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Figure 3. 33 x 32 Crosspoint Switch Memory Map
X X X X X X X X X X X
0 0 0 X
Address
IADDR
Data
UNICAST MODE (Address 0127)
BROADCAST
MULTICAST
BREAK
BANKSEL
ADVERT
0ADDR
Connect crosspoint input channel IADDR to output channel 0ADDR.
ADVERT overrides IADDR with the ADVERTISEP/N input.
X X X X X X X X X X X
0 0 1 X
Address
IADDR
Data
UNICAST MODE WITH BREAK (Address 128255)
BROADCAST
MULTICAST
BREAK
BANKSEL
ADVERT
0ADDR
Connect crosspoint input channel IADDR to output channel 0ADDR.
ADVERT overrides IADDR with the ADVERTISEP/N input.
X X X X X X X X X X X X X X X X
1 X X X
Address
IADDR
Data
BROADCAST MODE (Address 5121023)
BROADCAST
MULTICAST
BREAK
BANKSEL
ADVERT
Connect crosspoint input channel IADDR to all output channels.
ADVERT overrides IADDR with the ADVERTISEP/N input.
0 1 0
Address
IADDR
Data
MULTICAST MODE (Address 256383)
BROADCAST
MULTICAST
BREAK
BANKSEL
ADVERT
OUTPUT MASK
Connect crosspoint input channel IADDR to output channels as follows:
(1 in mask adds a connection, 0 keeps the previous connection)
ADVERT BANKSEL
0
0
1
1
0
1
0
1
IADDR to output mask selected channels 015
IADDR to output mask selected channels 1631
ADVERTISEP/N to output mask selected channels 015
ADVERTISEP/N to output mask selected channels 1631
0 1 1
Address
IADDR
Data
MULTICAST MODE WITH BREAK (Address 384511)
BROADCAST
MULTICAST
BREAK
BANKSEL
ADVERT
OUTPUT MASK
Connect crosspoint input channel IADDR to output channels as follows:
1 in mask adds a connection
0 breaks a connection (if the current IADDR matches the previous IADDR)
ADVERT BANKSEL
0
0
1
1
0
1
0
1
IADDR to output mask selected channels 015
IADDR to output mask selected channels 1631
ADVERTISEP/N to output mask selected channels 015
ADVERTISEP/N to output mask selected channels 1631
5
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
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Table 1. Pin Assignment and Descriptions
Note: Cavity up counter clockwise pin numbering orientation. (See Figure 5). For cavity down mounting, pin numbering will have
clockwise orientation.
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