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Datasheet: S2024B-8 (Applied Micro Circuits Corp.)

Bicmos Pecl Clock Generator Load Crossbow 32 X 32 800 Mbit/s Crosspoint Switch

 

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1
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
June 15, 1999 / Revision B
BiCMOS PECL CLOCK GENERATOR
FEATURES
· Full broadcast switching capability
· 32 x 32 crosspoint structure, expandable to 64 x
64 with no external components
· ECL 10K data path and TTL I/O for configuration
control provide high speed with easy interfacing to
slower-speed circuitry
· Up to 800 Mbit/s NRZ data rate in transparent
mode, 400-Mbit/s operation in synchronous mode
· 196-pin LDCC package
· Reconfigurable without disturbing operation
· Differential or single-ended clocking
APPLICATIONS
· Internet switches
· Digital video
· Digital demultiplexing
· Microwave or fiber-optic data distribution
· High-speed automatic test equipment
· Datacom or telecom switching
GENERAL DESCRIPTION
The S2024 "Crossbow" is a high-speed 32 x 32
crosspoint switch with full broadcast capability--any of
its 32 inputs can be connected independently to any or
all of its 32 outputs. In addition, the S2024 can be
expanded, through use of its expansion data inputs
(XDIN0­XDIN31), to a 64 x 64 crosspoint switch with
no external components. Further expansion is possible
with external addressing logic.
Two operating modes--synchronous (400 Mbit/s) and
transparent (800 Mbit/s)--provide maximum flexibility
across a range of applications. The 10K ECL logic data
path makes the part ideal for high-speed applications,
while the S2024's TTL addressing and control simplify
interfacing to slower-speed circuitry. The switch can be
completely reconfigured in only 4 ns without disturbing
switch operations.
Figure 1. Functional Block Diagram
XDINØ­31
DINØ­31
MDCLK
MDCLKN
32 x 32
CROSSPOINT
OUTPUT
LATCH
INPUT
LATCH
32
32
32
32
32
SDCLK
SDCLKN
DOUTØ­31
VBB2
VBB1
CNFGSTB
CONFIGURATION
LATCH
192
5:32
DECODE
EN
OUTADDØ­4
OAEN
CNFGCLK
RESET
INADDØ­5
32
6
5
192
32 X 6
REGISTER
FILE
LOAD
CLK
DATA
RST
®
DEVICE SPECIFICATION
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
2
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
June 15, 1999 / Revision B
OPERATING MODES
SYNCHRONOUS MODE
In synchronous mode, two clock signals, MDCLK for
data input and SDCLK for data output, provide the latch
enable strobes to allow the input data and output data
to be stored in 32-bit latches. The S2024 is capable of
400-Mbit/s operation in this mode. The data is latched
on the falling edge of SDCLK and MDCLK.
Inputs MDCLK/MDCLKN and SDCLK/SDCLKN can be
used as true differentials or as single-ended clocking
signals. Onboard voltage reference outputs VBB1 and
VBB2 allow single-ended clocking capability when con-
figured as shown in Figure 8.
TRANSPARENT MODE
In transparent, or asynchronous, mode, any data ap-
pearing at the input will be passed immediately through
to its designated output. Transparent transfer of data
through the latches takes place when both MDCLK and
SDCLK clock inputs are held high. In this mode the
S2024 is capable of up to a 800 Mbit/s NRZ data rate.
RECONFIGURATION MODE
The S2024 can be selectively reconfigured one output
at a time, or any number of outputs can be reconfigured
simultaneously. Configuration data is stored in 32 registers,
one register for each output data pin. The 6-bit content
of each register selects the input data pin which is to be
connected to that output data pin. To connect an output
to a given input, the output to reconfigure is selected
using OUTADD0­4 and OAEN to enable the appropriate
output configuration register. With the output configura-
tion register selected, the desired input pin connection
is provided on INADD0­5. The input pin selection on
INADD0­5 will be stored into the selected output con-
figuration register on the rising edge of CNFGCLK.
When the switch is to be reconfigured, the S2024 mini-
mizes the time required through the use of an additional
configuration latch. While the switch is operational (and
prior to the time at which it must be reconfigured) a new
set of input addresses can be loaded into the register
file. When all registers have been updated, the contents
of the registers are parallel-transferred to the configura-
tion latch, when CNFGSTB goes high. This process
allows a switch reconfiguration in just 4 ns.
Figure 2. Synchronous Mode
DINØ­31
MDCLK/N
SDCLK/N
XDINØ­31
DOUTØ­31
t
SUDI
t
HDI
A
B
C
A
B
A
B
MC
MPWH
MC
MPWL
t
OVRL
t
SUXDI
t
HXDI
t
SCKDO
Figure 3. Transparent Mode
CNFGSTB
A
B
C
D
E
A
B
C
D
E
DOUTØ­31
DINØ­31
t
DIDO
t
CFDO
A
B
C
D
E
XINØ­31
DI
MPW
t
XIDO
XI
MPW
Figure 4. Reconfiguration Mode
OUTADDØ­4
OAEN
SUOA
t
t
HOA
ADDRESS VALID
t
SUOAE
t
HOAE
CC
CC
INADDØ­5
CNFGCLK
CNFGSTB
VALID
MPWL
MPWH
SUCFC
t
CS
MPWH
SUIA
t
t
HIA
3
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
June 15, 1999 / Revision B
Table 1. Synchronous Mode Timing
Table 2. Transparent Mode Timing
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4
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
June 15, 1999 / Revision B
Table 3. Reconfiguration Timing (S2024B-8, S2024B-6)
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5
S2024
"CROSSBOW" 32 X 32 800 MBIT/S CROSSPOINT SWITCH
June 15, 1999 / Revision B
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f
o
n
o
i
t
c
e
l
e
s
e
h
t
s
e
l
b
a
n
e
,
h
g
i
h
n
e
h
W
.
e
l
b
a
n
e
s
s
e
r
d
d
a
t
u
p
t
u
O
.
r
e
t
s
i
g
e
r
n
o
i
t
a
r
u
g
i
f
n
o
c
t
u
p
t
u
o
e
t
a
i
r
p
o
r
p
p
a
K
L
C
D
M
N
K
L
C
D
M
L
C
E
I
6
6
5
6
.
s
t
u
p
n
i
l
a
i
t
n
e
r
e
f
f
i
d
e
u
r
T
.
)
a
t
a
d
t
u
p
n
i
(
s
t
u
p
n
i
k
c
o
l
c
h
c
t
a
l
r
e
t
s
a
M
.
2
B
B
V
d
n
a
1
B
B
V
h
t
i
w
d
e
d
n
e
-
e
l
g
n
i
s
d
e
s
u
e
b
n
a
C
Table 4. Pin Assignment and Descriptions
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