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Datasheet: S1201CONGO (Applied Micro Circuits Corp.)

STS-12c/STS-3c Pos/atm Sonet Mapper

 

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S1201
Congo Device Specification
Revision NC
August 2, 2000
Features
S1201 Block Diagram
General Description
CONGO
DEVICE SPECIFICATION
STS-12C/STS-3C POS/ATM SONET MAPPER
Part Number - S1201
Revision NC - August 2000
AMCC
Device Speicification Information - The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
· Processes SONET/SDH STS-12c/(STM-4/AU-4-4c) or
STS-3c/STM-1 data streams with full duplex mapping of
ATM cells or packets (PPP) into SONET/SDH payloads.
· Terminates & generates SONET/SDH section, line, & path
layers, with transport/section E1, E2, F1 and DCC over-
head interfaces in both transmit and receive directions.
· Provides an 8-bit parallel line-side interface operating at
19.44/77.76 MHz, and a 16-bit Utopia Level 2 or
POS-PHY
TM
system-side interface at 25/50 MHz.
· Generic 8-bit microprocessor interface for configuration,
control, and status monitoring.
· Scrambling/descrambling (1+X
6
+X
7
) of SONET/SDH
frame. Selectable self-synchronous scrambler implement-
ing (X
43
+1) polynomial for ATM/HDLC.
· Supports multiple devices sharing the same Utopia inter-
face when used in a multi-PHY configuration.
· Provides an 8-bit General Purpose I/O (GPIO) register.
· HDLC/PPP processing compliant with RFC 1619 & 1662.
· Compliant with SONET/ SDH specifications ANSI T1.105,
Bellcore GR-253-CORE and ITU G.707.
· Supports IEEE 1149.1 JTAG testing.
· Provides internal loopback paths for diagnostics.
· Packaged in a 208 pin PQFP.
· Implemented in 0.35 micron CMOS with 3.3v core and 5V
tolerant I/O.
The S1201 is a highly-integrated VLSI device that provides
full-duplex mapping of PPP encapsulated packets or ATM
cells into STS-12c/AU-4-4c or STS-3c/AU-4 payloads. The
S1201 supports full-duplex processing of SONET/SDH data
streams with full section, line, and path overhead process-
ing. The device supports framing pattern, scram-
bling/descrambling, alarm signal insertion/detection, and bit
interleaved parity (B1/B2/B3) processing. Serial interfaces for
SONET/SDH TOH overhead bytes are also provided.
The S1201 provides a line-side interface that can operate at
622.08 Mb/s (8-bit bus at 77.76 MHz) or 155.52 Mb/s (8-bit
bus at 19.44 MHz). For ATM applications, a UTOPIA Level 2
system interface, operating at either 25 or 50 MHz is pro-
vided. For Packet-over-SONET applications, a POS-PHY
TM
interface is provided.
ATM support includes insertion and extraction of ATM cells
into and out of the SONET/SDH SPE, scrambling/descram-
bling, header error control (HEC) detection and correction,
idle cell generation and filtering, and generation of perfor-
mance monitoring counts for TX, RX, ERR, dropped and idle
cells.
HDLC support includes framing, transparency processing,
optional 16/32 FCS processing, and self synchronous scram-
bling/descrambling (X
43
+1). It also supports a direct
flow-thru mode where the system data is passed directly to or
from the SPE.
UT
OP
IA
-2
/P
OS
-P
HY
TM
INT
E
RF
A
C
E
TX_SYS_DAT[15:0]
TX_ADR[4:0]
TX_CLK
TX_PRTY
TX_ENB
TX_SOC(P)
TX_CLAV(PTPA)
RX_SYS_DAT[15:0]
RX_ADR[4:0]
RX_CLK
RX_PRTY
RX_ENB
RX_SOC(P)
RX_CLAV(PRPA)
TX
CELL/PKT
FIFO
RX
CELL/PKT
FIFO
TX ATM/
HDLC
PROC
RX ATM/
HDLC
PROC
SCRAMBLE
DE-SCRAMBLE
RX ATM/
HDLC
COUNTERS
POINTER
INTERPRET
POH
MONITOR
TOH EXTRACT
TOH
MONITOR
RX
FRAMER
L
I
NE SIDE INT
E
RF
ACE
TX
FRAMER
TOH INSERT
SPE/VC & POH
GENERATE
T
X
_
S
DCC_
DA
T
A
T
X
_
S
DCC_
CL
K
T
X
_
L
DCC_
DA
T
A
TX
_L
D
C
C
_C
L
K
T
X
_E
1E
2F
1_C
LK
RX_
S
DCC_
DA
T
A
R
X
_
S
DCC_
CL
K
RX
_
L
DC
C_
DA
T
A
RX
_
L
DC
C_
CL
K
R
X
_E
1E
2F1
_
C
L
K
R
X
_E
1E
2F1
_
D
A
T
A
TX_STPA
RX_RVAL
RX_MOD
RX_EOP
RX_ERR
TX_MOD
TX_EOP
TX_ERR
D[7
:
0
]
A
DDR[8
:
0
]
CS
N
RDB
(
D
S
B
)
WRB
(
RWB)
RDYB
(
DT
AC
KB)
BUS
M
O
D
E
INT
B
MICROPROCESSOR I/F
JTAG PORT
GPIO REG
TD
O
TD
I
TC
K
TM
S
RT
S
B
G
P
P
IO[7:
0
]
TX_DATA[7:0]
TX_SONET_CLK
TX_FRAME_OUT
RX_DATA[7:0]
RX_SONET_CLK
RX_FRAME_IN
R
X
_
F
RA
M
E
_
O
UT
TX
_8K
_C
LK
RX_LOS
RX
_
L
AI
S
_
O
U
T
R
X
_LOF
_
OU
T
RX_
OOF
_
O
UT
TX
_F
R
A
ME
_IN
RST
B
APS
_
I
NT
B
TS
_E
N
T
X
_
E
1E
2F
1_D
A
T
A
AMCC
200 Brickstone Square, Andover, MA 01810 Ph: (978) 623-0009 Fax:(978) 623-0024
Revision NC - August 2000
DEVICE SPECIFICATION
S1201 STS-12c/STS-3c POS/ATM SONET Mapper
Overview and Applications
SONET Processing
The S1201 performs standard STS-3c/STM-1 or
STS-12c/(STM-4/AU-4-4c) processing for both the transmit
and receive directions. ATM cells or PPP packets are
mapped into the SONET/SDH SPE/VC, the POH, TOH/SOH
are inserted, and the resulting STS frame is transmitted in
byte wide format to the line-side interface. The reverse pro-
cess occurs when receiving data from the line-side. A TOH
interface provides direct add/drop capability for E1, E2, F1, &
both Section and Line DCC channels. The S1201 also
includes a clear channel mode that enables the direct trans-
mission of system payload from the system interface to the
line-side interface.
ATM Processing
When configured for ATM cell processing, the S1201's trans-
mit ATM processor will perform all necessary cell encapsula-
tion including HEC generation, cell level scrambling (X
43
+1),
and idle cell insertion to adapt the cell rate to the SPE. When
receiving data from the line side, it performs cell delineation,
Rx header control, descrambling, and receive cell rate adap-
tation. The S1201 also provides a full suite of status and con-
trol registers accessible via the microprocessor.
PPP/HDLC Processing
When configured for POS mode, the S1201's transmit HDLC
processor provides the insertion of HDLC framed packets
into the STS SPE. It will perform PPP packet framing,
inter-frame fill and Tx FIFO error recovery. In addition, it
optionally performs payload scrambling (X
43
+1), performs
transparency processing as required by RFC 1662 and will
optionally generate a 16/32 bit CRC.
The receive HDLC processor provides for the extraction of
HDLC frames, transparency removal, de-scrambling (if
enabled), FCS error checking and optionally deletes the
HDLC control and address fields. The S1201 also provides a
robust set of counters and status/control registers for perfor-
mance monitoring via the microprocessor.
Line-side Interface
On the line-side, the S1201 supports an 8-bit parallel inter-
face which operates at 77.76/19.44 MHz when the device is
configured for STS-12/STS-3. The device is typically con-
nected to a parallel-to-serial converter, which is in turn con-
nected to an electrical-to-optical converter for interfacing to
the fiber optic interface. (See figure below.)
System Interface
The S1201 interface to the system link-layer device is via a
Utopia Level-2 compliant interface when operating in ATM
mode, and a POS-PHY
TM
compatible interface when operat-
ing in Packet-Over-SONET mode. The interface operates at
25/50 MHz, as either 8 or 16 bits, in either Utopia or
POS-PHY
TM
mode.
Microprocessor Interface
An 8-bit microprocessor interface is provided for device con-
trol and monitoring. The interface supports both Intel and
Motorola type microprocessors, and is capable of operating
in either an interrupt driven or polled-mode configurations.
Applications
ATM switches, Routers, IP switches, Virtual Networks.
Typical Application: S1201 in 622 Mb/s ATM or POS System
TX_DATA[7:0]
TX_SONETCLK
RX_SONETCLK
RX_DATA[7:0]
P/S & S/P
SONET XCVR
with
Clk Recovery
SerRxDħ
SerTxDħ
Microprocessor
Control
Control
AMCC S3032
Sumitomo SDM7202
HP HFCT5208
Reference
Clock
Fiber Optic
Transceiver
SONET
Line Side
Interface
RX_LOS
S1201
AMCC
Addr
Data
8
9
TX_CLK
TX_SYS_DAT[15:0]
RX_CLK
RX_SYS_DAT[15:0]
Utopia Level-2
or
POS-PHY
TM
System Interface
TOH Insertion
and Extraction
AMCC 5
Revision NC - August 2000
DEVICE SPECIFICATION
S1201 STS-12c/STS-3c POS/ATM SONET Mapper
Table of Contents
1.0 Applicable Documents ................................................................................................................. 11
2.0 Pin Assignments and Descriptions ........................................................................................... 12
Table 1: Line Side Interface Pin Descriptions ........................................................................... 13
Table 2: Utopia and POS-PHYTM Pin Descriptions ................................................................. 14
Table 3: Transport Overhead Pin Descriptions ........................................................................ 19
Table 4: Microprocessor Interface Pin Descriptions ................................................................. 20
Table 5: JTAG Interface Pin Description .................................................................................. 21
Table 6: Miscellaneous Pin Descriptions .................................................................................. 22
3.0 Mechanical Packaging Information ............................................................................................. 24
4.0 Functional Descriptions ............................................................................................................... 25
4.1 Conventions .............................................................................................................................. 25
4.2 Monitors and Control Interface .................................................................................................. 25
4.3 Configuration ............................................................................................................................. 26
4.4 SONET/SDH Processing .......................................................................................................... 26
4.4.1 Receive SONET/SDH Processing .......................................................................................... 26
Table 7: TX/RX_SIG_MODE Values ........................................................................................ 26
4.4.2 Transmit SONET/SDH Processing ......................................................................................... 27
4.5 HDLC/ATM Processing ............................................................................................................. 28
4.5.1 Receive HDLC Processor ....................................................................................................... 28
4.5.2 Receive ATM Processor ......................................................................................................... 29
4.5.3 Transmit HDLC Processor ...................................................................................................... 30
4.5.4 Transmit ATM Processor ........................................................................................................ 30
4.6 FCS Polynomials ...................................................................................................................... 31
5.0 Processing of Data in the Transmit Direction ............................................................................ 32
5.1 Transmit FIFO Interface ............................................................................................................ 32
5.1.1 Transmit Data Parity Check .................................................................................................... 32
5.1.2 Transmit FIFO......................................................................................................................... 32
5.1.3 POS Errored Packet Handling ................................................................................................ 32
5.1.4 Line Side Cell/Packet Loopback ............................................................................................. 33
5.2 Transmit HDLC Processing ...................................................................................................... 33
5.2.1 Encapsulation of Packets in HDLC Frame.............................................................................. 34
5.2.2 Address and Control Fields..................................................................................................... 34
5.2.3 Frame Check Sequence (FCS) Field...................................................................................... 35
5.2.4 Transparency .......................................................................................................................... 35
Table 8: Octet Values Handled by Transparency Processing .................................................. 35
5.2.5 SPE Creation .......................................................................................................................... 36
5.3 Transmit ATM Processing ......................................................................................................... 37
5.3.1 Transmit Data HEC Check...................................................................................................... 37
5.3.2 Transmit Valid Cell Count ....................................................................................................... 37
5.3.3 SPE Payload Creation ............................................................................................................ 37
5.3.4 Header Error Control (HEC) Sequence Generation................................................................ 38
Table 9: Pattern for Default Idle Cell ........................................................................................ 38
6 AMCC
Table of Contents (continued)
Revision NC - August 2000
DEVICE SPECIFICATION
S1201 STS-12c/STS-3c POS/ATM SONET Mapper
Table 10: ATM Cell Header Format .......................................................................................... 38
5.4 Scrambling ................................................................................................................................ 39
5.4.1 ATM Scrambler Operation ...................................................................................................... 39
5.4.2 HDLC Scrambler Operation .................................................................................................... 39
5.4.3 Direct SPE Mapping Scrambler Operation ............................................................................. 39
5.5 SPE/VC Generation .................................................................................................................. 39
5.5.1 SPE/VC Structure ................................................................................................................... 39
5.5.2 POH ........................................................................................................................................ 40
Table 11: Path RDI Bit Values .................................................................................................. 41
5.6 SONET/SDH Frame Generation ............................................................................................... 42
5.6.1 Frame Alignment..................................................................................................................... 42
Table 12: STS-12c/STM-4 Provisioning for TX_FOUT_BYTE_TYPE[1:0] and
TX_FOUT_BYTE_NUMBER[3:0] ........................................................................................ 43
Table 13: STS-3c/STM-1 Provisioning for TX_FOUT_BYTE_TYPE[1:0] and
TX_FOUT_BYTE_NUMBER[3:0] ........................................................................................ 43
Table 14: Data on TX_DATA[7:0] ............................................................................................. 43
5.6.2 Payload Generation ................................................................................................................ 44
5.6.3 TOH/SOH Generation............................................................................................................. 44
Table 15: STS-12c/STM-4 TOH/SOH ...................................................................................... 44
Table 16: STS-3c/STM-1 TOH/SOH ........................................................................................ 45
5.6.4 Scrambling .............................................................................................................................. 48
6.0 Processing of Data in the Receive Direction ............................................................................. 49
6.1 T-to-R Loopback and LOC ........................................................................................................ 49
6.2 STS-12c/STM-4 Framer ............................................................................................................ 49
6.2.1 Framer Enabled Operation ..................................................................................................... 49
6.2.2 Framer Bypass Operation....................................................................................................... 49
Table 17: STS-12c/STM-4 Provisioning for RX_FIN_BYTE_TYPE[1:0] and
RX_FIN_BYTE_NUMBER[3:0] ............................................................................................ 50
Table 18: STS-3c/STM-1 Provisioning for RX_FIN_BYTE_TYPE[1:0] and
RX_FIN_BYTE_NUMBER[1:0] ............................................................................................ 50
6.2.3 Descrambling .......................................................................................................................... 51
6.2.4 B1 Monitor............................................................................................................................... 51
6.3 Transport Overhead Monitoring ................................................................................................ 51
6.3.1 J0 Monitoring .......................................................................................................................... 52
6.3.2 BIP-96 (B2) Checking ............................................................................................................. 52
6.3.3 K1K2 Monitoring ..................................................................................................................... 53
6.3.4 S1 Monitoring.......................................................................................................................... 54
6.3.5 M1 Monitoring ......................................................................................................................... 54
6.4 Transport Overhead Drop ......................................................................................................... 54
6.4.1 Orderwire (E1 and E2) and Section User Channel (F1) ......................................................... 54
6.4.2 Data Communications Channels, DCC, (D1-D12).................................................................. 54
6.5 Pointer State Determination ...................................................................................................... 54
6.5.1 State Transition Rules............................................................................................................. 54
6.5.2 State of STS-12c/AU-4-4c [STS-3c/AU-4] Pointer.................................................................. 55
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