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Datasheet: NILE (Applied Micro Circuits Corp.)

Sts-12 Atm/ds3 Sonet Mapper

 

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AMCC
S1202
Nile Device Specification
Revision NC
June 14, 2000
Features
S1202 Block Diagram
General Description
NILE
STS-12 ATM/DS3 SONET MAPPER
Part Number S1202
Revision NC - June 2000
AMCC
DEVICE SPECIFICATION
Device Specification Information - The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
· Processes valid combinations of SONET/SDH
STS-12c/AU-4-4c, STS-3c/AU-4, or STS-1 tributaries
within an STS-12/STM-4.
· Terminates and generates SONET/SDH section, line, and
path layers.
· Provides DS3 mapping and demapping for 12 STS-1s and
supports clear channel DS3.
· Supports ATM payload mapping into STS-12c/AU-4-4c &
STS-3c/AU-4, as well as direct ATM or ATM PLCP for DS3
tributaries.
· Supports M23 and C-Bit parity clear channel DS3 map-
ping, as well as clear channel DS3 transparent
passthrough mode.
· Provides a 77.76 MHz 8-bit bus interface on the
SONET/SDH side in both the TX and RX directions.
· Provides a 50 MHz 16-bit Utopia Lvl 2 interface on the sys-
tem side in both the TX and RX directions.
· Programmable Utopia addresses to support multi-PHY
operation.
· Generic 8-bit microprocessor interface for configuration
and status monitoring.
· Supports IEEE 1149.1 JTAG testing.
· Packaged in a 388 pin BGA.
· Implemented in 3.3V with 5V tolerant I/O.
· Loopback capability for SONET/SDH, DS3 and ATM.
The S1202 is a highly integrated chip that implements
SONET/SDH processing and ATM mapping functions for
STS-12/STM-4 data streams. In addition, it supports DS3
tributaries, in an STS-1 SPE, with provisionable support for
M23 or C-bit parity OH, as well as clear channel
pass-through, direct mapping of ATM cells, or ATM PLCP
mapping. The S1202 is SONET and SDH standards compli-
ant with Bellcore GR-253 and ANSI T1.105, and ITU G.707,
respectively. The S1202 is also DS3 standards compliant
with Bellcore GR-499 and ANSI T1.107-1995 and ATM stan-
dards compliant with Utopia Specification Level 2.
The S1202 supports full-duplex processing of SONET/SDH
data streams with section, line, & path overhead processing.
The device supports framing, scrambling/descrambling,
alarm signal insertion/detection, and bit interleaved parity
(B1/B2/B3) processing. Serial interfaces for E1, E2, F1 and
Line and Section DCC are also provided.
A general purpose 8-bit microprocessor interface is provided
for device initialization, control, and monitoring. The interface
supports both Intel and Motorola type microprocessors, and
is capable of operating in either an interrupt driven or
polled-mode configuration.
Applications
·
ATM switches
·
Packet over SONET Routers and Switches
·
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers and Digital Cross Connects
·
Test equipment
TX_ATM_DAT[15:0]
POINTER
INTERPRET
POH
MONITOR
TOH DROP
TOH
MONITOR
RX
FRAMER
L
I
NE SIDE INT
E
RF
ACE
TX
FRAMER
TOH INSERT
SPE/VC
GENERATE
T
X
_
S
DCC_
DA
T
A
TX
_S
D
C
C
_
C
LK
T
X
_
L
DCC_
DA
T
A
T
X
_
L
DCC_
CL
K
TX
_E
1E
2F1
_
C
L
K
RX_
S
DCC_
DA
T
A
RX_
S
DC
C_
CL
K
RX_
L
DCC_
DA
T
A
RX_
L
DCC_
CL
K
R
X
_E
1
E
2F
1_C
L
K
R
X
_E
1
E
2F
1_D
A
T
A
D
[
7:0]
ADDR[1
1
:0
]
CS
N
RDB(
D
SB)
W
R
B(
R
W
B)
R
D
Y
B(
DT
AC
K
B
)
BU
SM
O
D
E
INT
B
MICROPROCESSOR I/F
JTAG PORT
GPIO REG
TD
I
TC
K
TM
S
TR
TS
B
GP
P
IO[1
5:0]
TX_DATA[7:0]
TX_CLK78
TX_FRAME_IN
RX_DATA[7:0]
RX_CLK78
RX_FRAME_OUT
T
X
_
8
K
_
CLK
RX_EXTLOS
RX
_
L
AI
S
_
O
U
T
R
X
_LOF
_
OU
T
RX_
OOF
_
O
UT
RST
B
APS
_
I
NTB
TS
_E
N
T
X
_
E
1E
2F
1_D
A
T
A
1
12
DS3
1
12
DS3
FR
PRBS
Det
FR
PRBS
Gen
DL
Insert
TX
_D
L_
D
A
T
A
T
X
_D
L_E
N
B
DL Drop
R
X
_D
L_D
A
T
A
R
X
_D
L_
E
N
B
FEBE
TX_DS3[1:4][1:3]DATA
RX_DS3[1:4][1:3]FIFO[1:0]
1
12
DS3
Dmap
1
12
DS3
Map
1
12
PLCP
1
12
1
12
ATM
1
12
ATM
Proc
Proc
Proc
PLCP
Proc
TD
O
Clear Channel DS3
Clear Channel DS3
TX_PRTY
TX_SOC
TX_CLK
TX_ENB
TX_ADR[4:0]
TX_CLAV[3:0]
RX_ATM_DAT[15:0]
RX_PRTY
RX_SOC
RX_CLK
RX_ENB
RX_ADR[4:0]
RX_CLAV[3:0]
RX_DS3[1:4][1:3]DATA
RX_DS3_x_y_GAP_CLK
T
X
_F
RA
M
E
_O
U
T
RX_FRAME_IN
TX_DS3[1:4][1:3]CLK
RX_DS3_x_y_CLK
D
L_C
LK
DL
_
S
YNC
TX_DS3[1:4][1:3]FIFO
TX_DS3[1:4][1:3]X1_IN
RX_DS3[1:4][1:3]X1_OUT
1
12
TX
FIFO
1
12
RX
FIFO
RX
Utopia
I/F
Utopia
TX
I/F
200 Brickstone Square, Andover, MA 01810 Ph: 978/623-0009 Fax:978/623-0024
AMCC
S1202 STS-12 ATM/DS3 SONET MAPPER
Revision NC - June 2000
DEVICE SPECIFICATION
Overview and Applications
SONET Processing
The S1202 implements SONET/SDH processing and ATM
mapping functions for STS-12/STM-4 data streams. It can
support any combination of STS-12c, STS-3c, or STS-1 sig-
nals within an STS-12, or any combination of AU-4-4c or
AU-4 signals within an STM-4. In addition, it can support DS3
tributaries, in SONET, with provisionable support for clear
channel passthrough, direct mapping of ATM cells, or ATM
PLCP mapping. A TOH/SOH interface provides direct
add/drop capability for E1, E2, F1, and both Section and Line
DCC channels.
On the transmit side the S1202 generates section, line, &
path overhead. It performs framing pattern insertion (A1, A2),
scrambling, alarm signal insertion, and generates section,
line and path Bit Interleaved Parity (B1/B2/B3) for far-end
performance monitoring.
On the receive side the S1202 processes section, line, & path
overhead. It performs payload framing (A1, A2), descram-
bling, alarm detection, Bit Interleaved Parity monitoring
(B1/B2/B3), and error count accumulation for performance
monitoring.
ATM Processing
When configured for ATM cell processing, the S1202 transmit
ATM processor will perform all necessary cell encapsulation
including HEC generation, cell level scrambling (X
43
+1), and
idle cell insertion to adapt the cell rate to the SPE. When
receiving data from the line side, it performs cell delineation,
Rx header control, descrambling, and receive cell rate adap-
tation.
DS3 Processing
The S1202 provides DS3 mapper and de-mapper functions.
The DS3 mapper accepts data from an external DS3 input,
from looped-back DS3 tributaries, or from internal DS3 frame
generators. The internal DS3 frame generators are used for
ATM, PLCP, or PRBS data. The S1202 maps the data into
STS-1 SONET payloads.
The S1202 DS3 de-mapper support includes the ability to
extracts DS3 or ATM data from the SONET signal. DS3 sig-
nals can contain ATM, PLCP, or clear channel DS3 data. For
ATM or PLCP data, the S1202 frames on the DS3 and
extracts these signals from the DS3 payload. For clear chan-
nel DS3 data, the S1202 generates RX serial (NRZ) data sig-
nals smoothed to match a DS3 clock input that is provided to
the device, as well as a FIFO Fill Indication, provided for
phase lock loop adjustment. The S1202 also provides full
DS3 framing, monitoring, and extraction for full DS3 support.
Line-side Interface
On the line-side, the S1202 supports an 8-bit parallel inter-
face which operates at 77.76 MHz. The device is typically
connected to a parallel-to-serial converter, which is in turn
connected to an electrical-to-optical converter for interfacing
to the fiber optic interface. (See figure below.)
System Interface
The S1202 supports a UTOPIA Level 2 interface, operating at
50 Mb/s, for providing ATM cell transfers to/from the system
interface. The S1202 also supports up to 12 DS3 tributaries.
For clear channel DS3 data, the S1202 generates RX serial
(NRZ) data signals smoothed to match a DS3 clock input that
is provided to the device, as well as a FIFO Fill Indication,
provided for phase lock loop adjustment.
TX_DATA[7:0]
TX_CLK78
RX_CLK78
RX_DATA[7:0]
P/S & S/P
SONET XCVR
with
Clk Recovery
SerRxDħ
SerTxDħ
Microprocessor
Control
Control
AMCC S3032
Sumitomo SDM7202
HP HFCT5208
Reference
Clock
Fiber Optic
Transceiver
SONET
Line Side
Interface
RX_LOS
S1202
AMCC
Addr
Data
8
12
TX_CLK
TX_SYS_DAT[15:0]
RX_CLK
RX_SYS_DAT[15:0]
Utopia Level-2
System Interface
TOH Insertion
and Extraction
ATM Switch
OR
U
T
O
P
I
A
DS3
DS3 Clear Channel for
TX_DS3_[1:12]_DATA
RX_DS3_[1:12]_DATA
RX_DS3_[1:12]_GAP/SM_CLK
RX_DS3_[1:12]_FIFO_[1:0]
TX_DS3_[1:12]_CLK
Packet over SONET Application
Multi
Channel
HDLC
Processor
IP ROUTER
Switching/
Routing
Logic
Channelized 622 Mb/s ATM Application
TYPICAL APPLICATIONS
AMCC v
Table of Contents
S1202 STS-12 ATM/DS3 SONET MAPPER
Revision NC - June 2000
DEVICE SPECIFICATION
1.0 Applicable Documents .....................................................................................................11
2.0 Pin Assignments and Description ..................................................................................12
Table 1: Line Side SONET Interface ............................................................................................... 13
Table 2: Utopia Interface ................................................................................................................. 14
Table 3: DS3 Interface..................................................................................................................... 17
Table 4: Datalink Interface............................................................................................................... 22
Table 5: Transport Overhead Interface............................................................................................ 28
Table 6: Microprocessor Interface ................................................................................................... 29
Table 7: JTAG/Test Interface ........................................................................................................... 30
Table 8: GPIO interface Pins ........................................................................................................... 31
3.0 Packaging Information .....................................................................................................33
Table 9: Mechanical Specifications ................................................................................................. 34
4.0 Functional Descriptions .................................................................................................. 35
4.1 Common Conventions .............................................................................................................. 35
4.2 Multiplexing and Tributary Indexing Convention ....................................................................... 35
4.3 Monitors and Control Interface .................................................................................................. 36
Table 10: SONET, SDH, and DS3 Register Index Values ............................................................... 36
4.4 Configuration ............................................................................................................................. 37
4.4.1 TX Configuration ............................................................................................................... 37
Table 11: Transmit Configurationa................................................................................................... 37
4.4.2 RX Configuration............................................................................................................... 39
Table 12: Transmit DS3 Configuration
a ..............................................................................................................................................39
4.5 SONET/SDH Processing .......................................................................................................... 40
4.5.1 Receive SONET/SDH Processing .................................................................................... 40
4.5.2 Transmit SONET/SDH Processing ................................................................................... 41
4.5.3 Receive DS3 Processing .................................................................................................. 42
4.5.4 Transmit DS3 Processing ................................................................................................. 43
4.6 PLCP Processing ...................................................................................................................... 43
4.6.1 Receive PLCP Processor ................................................................................................. 43
4.6.2 Transmit PLCP Processor ................................................................................................ 43
4.7 ATM Processor ......................................................................................................................... 44
4.7.1 Receive ATM Processor ................................................................................................... 44
4.7.2 Transmit ATM Processor .................................................................................................. 44
5.0 Processing of Data in the Transmit Direction ............................................................... 45
5.1 System Interface ....................................................................................................................... 45
5.1.1 Utopia Level 2 Interface .................................................................................................... 45
5.1.2 DS3 System Interface ....................................................................................................... 45
5.1.3 FIFO Operation ................................................................................................................. 45
5.1.4 Transmit Valid Cell Count ................................................................................................. 46
5.1.5 Line Side Loopback .......................................................................................................... 46
5.2 Transmit ATM Processor .......................................................................................................... 46
5.2.1 SPE or DS3 Payload Creation .......................................................................................... 47
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